HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS

• US 20190319048A1
• Filed: 06/20/2019
• Published: 10/17/2019
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Smith, Elliot John, Chan, Nigel, Kenkare, Nilesh
• Granted Patent: US 10,811,433 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Abstract

One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

Claims

1. A semiconductor device, comprising

a semiconductor-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer positioned on said semiconductor bulk substrate and a semiconductor layer positioned on said buried insulation layer;

and

a first transistor device, wherein said first transistor device comprises a first channel region formed in said semiconductor bulk substrate and a first gate insulation layer formed above said first channel region, said first gate insulation layer comprising a part of said buried insulation layer and an oxidized part of said semiconductor layer.

2. The semiconductor device of claim 1, wherein said first transistor device comprises a first gate and further comprising a second transistor device comprising a second channel region formed in one of said semiconductor bulk substrate and said semiconductor layer and a second gate and wherein said first and the second gates are made from a same gate layer.

3. The semiconductor device of claim 1, wherein said first gate insulation layer has a thickness of more than 35 nm.

4. A semiconductor device, comprising

a semiconductor-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer positioned on said semiconductor bulk substrate and a semiconductor layer positioned on said buried insulation layer;

a first transistor device and a second transistor device;

wherein said first transistor device comprises a first channel region formed in said semiconductor bulk substrate, first raised source and drain regions formed on said semiconductor bulk substrate, and a first gate insulation layer formed above said first channel region, wherein said first gate insulation layer comprises at least a part of said buried insulation layer and an oxidized part of said semiconductor layer; and

said second transistor device comprises a second channel region formed in one of said semiconductor bulk substrate and said semiconductor layer, second raised source and drain regions formed on said one of said semiconductor bulk substrate and said semiconductor layer and a second gate insulation layer formed above said second channel region.

5. The semiconductor device of claim 4, further comprising:

a third transistor device comprising a third channel region formed in the other one of said semiconductor bulk substrate and said semiconductor layer, third raised source and drain regions formed on said other one of said semiconductor bulk substrate and said semiconductor layer and a third gate insulation layer formed on said third channel region.

6. The semiconductor device of claim 5, wherein said second and third gate insulation layers are formed from a same dielectric layer and wherein said first gate insulation layer comprises a part of said dielectric layer.

7. A semiconductor device, comprising

a semiconductor-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer positioned on said semiconductor bulk substrate and a semiconductor layer positioned on said buried insulation layer, said buried insulation layer having a first thickness;

and

a first transistor device, wherein said first transistor device comprises a first channel region formed in said semiconductor bulk substrate and a first gate insulation layer formed above said first channel region, said first gate insulation layer having a second thickness that is greater than said first thickness.

8. The semiconductor device of claim 7, wherein said first gate insulation layer comprises a portion of said buried insulation layer and additional gate insulation material positioned on said portion of said buried insulation layer.

9. The semiconductor device of claim 7, wherein said first gate insulation layer comprises a portion of said buried insulation layer and an oxidized part of said semiconductor layer.

10. The semiconductor device of claim 8, wherein said first transistor device comprises a first gate and further comprising a second transistor device comprising a second channel region formed in one of said semiconductor bulk substrate and said semiconductor layer and a second gate, wherein said first and the second gates are made from a same gate layer.

11. The semiconductor device of claim 9, wherein said first transistor device comprises a first gate and further comprising a second transistor device comprising a second channel region formed in one of said semiconductor bulk substrate and said semiconductor layer and a second gate, wherein said first and the second gates are made from a same gate layer.

12. The semiconductor device of claim 7, wherein said first transistor device comprises a first gate and further comprising a second transistor device comprising a second channel region formed in one of said semiconductor bulk substrate and said semiconductor layer and a second gate, wherein said first and the second gates are made from a same gate layer.

13. The semiconductor device of claim 10, further comprising a second gate insulation layer formed above said second channel region, said second gate insulation layer having a thickness that is less than said second thickness.

14. The semiconductor device of claim 11, further comprising a second gate insulation layer formed above said second channel region, said second gate insulation layer having a thickness that is less than said second thickness.

15. The semiconductor device of claim 12, further comprising a second gate insulation layer formed above said second channel region, said second gate insulation layer having a thickness that is less than said second thickness.