INTEGRATED RF FRONT END SYSTEM

• US 20190319093A1
• Filed: 03/22/2019
• Published: 10/17/2019
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph, Doherty, Mark M.
• Granted Patent: US 10,522,617 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0821 : Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0826 : Pedestal collectors
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66242 : Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/737 : Hetero-junction transistors
• CPC Class Codes: H01L 29/7371 : Vertical transistors
• CPC Class Codes: H01L 29/7378 : comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01Q 1/24 : with receiving set
• CPC Class Codes: H03F 2200/222 : A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/318 : A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only

Abstract

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Claims

1. (canceled)

2. A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:

a semiconductor wafer including a high-resistivity substrate of a first doping type;

a transistor sub-collector region of a second doping type disposed at least partially below a top plane of the semiconductor wafer, the transistor sub-collector region forming a portion of a transistor;

a low-resistivity epitaxial layer of the second doping type disposed above the top plane of the semiconductor wafer;

a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the transistor; and

a trench between the transistor sub-collector region and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.

3. The multi-layer semiconductor package of claim 2 wherein the plurality of devices are implemented using heterogeneous semiconductor technologies.

4. The multi-layer semiconductor package of claim 2 wherein the transistor is a bipolar transistor.

5. The multi-layer semiconductor package of claim 2 wherein the trench is disposed immediately adjacent to the low-resistivity well preventing an occurrence of charge collection between the trench and the low-resistivity well.

6. The multi-layer semiconductor package of claim 2 wherein the first doping type is p-type and the second doping type is n-type.

7. The multi-layer semiconductor package of claim 2 wherein the transistor sub-collector region is heavily doped and the low-resistivity epitaxial layer is lightly doped.

8. The multi-layer semiconductor package of claim 2 wherein the high-resistivity substrate is lightly doped.

9. The multi-layer semiconductor package of claim 2 wherein the high-resistivity substrate is formed from bulk silicon and the transistor sub-collector is formed from silicon germanium.

10. The multi-layer semiconductor package of claim 2 wherein the transistor forms a part of a switch circuit, a low noise amplifier circuit, or a mixer circuit.

11. The multi-layer semiconductor package of claim 2 further comprising a high-resistivity region disposed adjacent to the low-resistivity well, the low-resistivity well positioned between the high-resistivity region and the trench.

12. A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:

a semiconductor wafer including a high-resistivity substrate of a first doping type;

a triple-well transistor disposed at least partially below a top plane of the semiconductor wafer;

a low-resistivity epitaxial layer of a second doping type disposed above the top plane of the semiconductor wafer;

a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor; and

a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.

13. The multi-layer semiconductor package of claim 12 wherein the triple-well transistor includes a first well of the first doping type with a top surface within the top plane of the semiconductor wafer.

14. The multi-layer semiconductor package of claim 13 wherein the triple-well transistor includes a deep well disposed between the first well and the high-resistivity substrate.

15. The multi-layer semiconductor package of claim 12 wherein the triple-well transistor is a field-effect transistor.

16. The multi-layer semiconductor package of claim 12 wherein the high-resistivity substrate is formed from bulk silicon and the triple-well transistor is formed from silicon germanium.

17. The multi-layer semiconductor package of claim 12 wherein the trench is disposed immediately adjacent to the low-resistivity well preventing an occurrence of charge collection between the trench and the low-resistivity well.

18. A method of fabricating a multi-layer semiconductor package supporting a plurality of devices, the method comprising:

forming a high-resistivity substrate of a first doping type within a semiconductor wafer;

forming a triple-well transistor on the high-resistivity substrate, at least a portion of the triple-well transistor disposed below a top plane of the semiconductor wafer;

forming a low-resistivity epitaxial layer of a second doping type above the top plane of the semiconductor wafer;

implanting a low-resistivity well within the semiconductor wafer, the low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor; and

etching a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.

19. The method of claim 18 wherein said forming the low-resistivity epitaxial layer includes out-diffusing arsenic from the multi-layer semiconductor package.

20. The method of claim 18 wherein the trench is etched immediately adjacent to the low-resistivity well preventing an occurrence of charge collection between the trench and the low-resistivity well.

21. The method of claim 18 wherein the high-resistivity substrate is formed from a silicon seed.