INTEGRATED RF FRONT END SYSTEM
Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.
- 1. (canceled)
- 2. A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:
a semiconductor wafer including a high-resistivity substrate of a first doping type; a transistor sub-collector region of a second doping type disposed at least partially below a top plane of the semiconductor wafer, the transistor sub-collector region forming a portion of a transistor; a low-resistivity epitaxial layer of the second doping type disposed above the top plane of the semiconductor wafer; a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the transistor; and a trench between the transistor sub-collector region and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.
- View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
- 12. A multi-layer semiconductor package supporting a plurality of devices, the multi-layer semiconductor package comprising:
a semiconductor wafer including a high-resistivity substrate of a first doping type; a triple-well transistor disposed at least partially below a top plane of the semiconductor wafer; a low-resistivity epitaxial layer of a second doping type disposed above the top plane of the semiconductor wafer; a low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor; and a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.
- View Dependent Claims (13, 14, 15, 16, 17)
- 18. A method of fabricating a multi-layer semiconductor package supporting a plurality of devices, the method comprising:
forming a high-resistivity substrate of a first doping type within a semiconductor wafer; forming a triple-well transistor on the high-resistivity substrate, at least a portion of the triple-well transistor disposed below a top plane of the semiconductor wafer; forming a low-resistivity epitaxial layer of a second doping type above the top plane of the semiconductor wafer; implanting a low-resistivity well within the semiconductor wafer, the low-resistivity well providing at least one device from the plurality of devices with at least partial electrical isolation from the triple-well transistor; and etching a trench between the triple-well transistor and the low-resistivity well, the trench configured to impede a movement of carriers in the high-resistivity substrate.
- View Dependent Claims (19, 20, 21)
This disclosure is a continuation of and claims priority to U.S. application Ser. No. 15/798,129 filed Oct. 30, 2017 and titled “INTEGRATED RF FRONT END SYSTEM,” the disclosure of which is hereby expressly incorporated by reference herein in its entirety and which is a continuation of and claims priority to U.S. application Ser. No. 15/216,620 filed Jul. 21, 2016 and titled “INTEGRATED RF FRONT END SYSTEM,” the disclosure of which is hereby expressly incorporated by reference herein in its entirety and which is a continuation of and claims priority to U.S. application Ser. No. 14/703,465 filed May 4, 2015 and titled “INTEGRATED RF FRONT END SYSTEM,” the disclosure of which is hereby expressly incorporated by reference herein in its entirety and which is a continuation of U.S. application Ser. No. 13/536,749 filed Jun. 28, 2012 and titled “INTEGRATED RF FRONT END SYSTEM,” the disclosure of which is expressly incorporated by reference herein in its entirety.
The present disclosure generally relates to the field of electronics, and more particularly, to radio frequency front-end modules.
Radio frequency (RF) is a common term for a range of frequency of electromagnetic radiation typically used to produce and detect radio waves. Such a range can be from about 30 kHz to 300 GHz. Wireless communication devices often include front-end circuitry for processing or conditioning RF signals at an incoming or outgoing frequency or signal port. RF front-end modules may be components of receiver, transmitter, or transceiver systems associated with a wireless device.
RF front-end design may include a number of considerations, including complexity, substrate compatibility, performance, and integration.
Certain embodiments provide functional integration of all necessary and desirable building blocks of the front-end circuitry onto a single BiCMOS technology platform featuring a high-resistivity substrate. For example, FEMs may be fully integrated using SiGe BiCMOS technology with high-resistivity layers. An integrated front-end module comprising:
Certain embodiments disclosed herein provide a silicon substrate having a high-resistivity portion and an SiGe bipolar transistor disposed on the substrate above the high-resistivity portion. The front-end module may include a switch disposed on the substrate. The bipolar transistor may be part of a power amplifier module. Such power amplifier module may include, for example, a first power amplifier device configured to amplify RF signals in a first frequency band and a second power amplifier device configured to amplify RF signals in a second frequency band separate from the first frequency band. A signal at 2.4 GHz may be included in the first frequency band, and a signal at 5 GHz may be included in the second frequency band.
The first power amplifier device may be configured to amplify RF signals in accordance with IEEE 802.11b/g specifications and the second power amplifier device may be configured to amplify RF signals in accordance with IEEE 802.11a/ac specifications. Furthermore, the power amplifier module may include a multi-stage power amplifier. For example, the first power amplifier device may be a two-stage power amplifier and the second power amplifier device may be a three-stage power amplifier.
The front-end module may include various other devices. For example, the front-end module may include at least one filter device, or a power detector module at least partially coupled to the power amplifier module. The front-end module may include at least one filter device. The front-end module may include a low-noise amplifier module. The low-noise amplifier module may include a low-noise amplifier bypass switch.
The high-resistivity portion may have a resistivity value greater than approximately 500 Ohm*cm. For example, the high-resistivity portion may have a resistivity of approximately 1 kOhm*cm or greater. Furthermore, the switch may be an SP4T switch, SP5T switch, or other type of switch.
Certain embodiments disclosed herein provide a method of fabricating an integrated front-end module. The method may include providing at least a portion of a high-resistivity bulk silicon substrate and forming one or more bipolar transistors on the high-resistivity substrate. The method may further include implanting a low-resistivity region around the one or more bipolar transistors.
Certain embodiments disclosed herein provide a semiconductor die that includes a silicon substrate including a high-resistivity portion and being configured to receive a plurality of components. The die may further include RF front-end circuitry disposed on the substrate, the RF front-end circuitry including an SiGe bipolar transistor disposed above the high-resistivity portion. The RF front-end circuitry may be configured to process wireless signals in compliance with the IEEE 802.11ac wireless communication standard, or other 801.11 standards. Furthermore, the RF front-end circuitry includes a sixth-order SiGe power amplifier filter.
Certain embodiments disclosed herein provide a radio-frequency (RF) module including a packaging substrate configured to receive a plurality of components, a die mounted on the packaging substrate, the die having a high-resistivity substrate portion, a switch, a power amplifier including an SiGe bipolar transistor disposed above the high-resistivity substrate portion, and one or more passive devices, and a plurality of connectors configured to provide electrical connections between the die and the packaging substrate. The packaging substrate may have an area of less than 3.0 mm2 and may have a height of less than 0.5 mm.
Certain embodiments disclosed herein provide an RF device including a processor configured to process RF signals, RF front-end circuitry disposed on a substrate having a high-resistivity portion, the RF front-end circuitry including a switch, one or more passive devices, and a power amplifier including an SiGe bipolar transistor disposed above the high-resistivity portion, and an antenna in communication with at least a portion of the RF front-end circuitry to facilitate transmission and reception of the RF signals.
Various embodiments are depicted in the accompanying drawings for illustrative purposes, and should in no way be interpreted as limiting the scope of the inventions. In addition, various features of different disclosed embodiments can be combined to form additional embodiments, which are part of this disclosure. Throughout the drawings, reference numbers may be reused to indicate correspondence between reference elements.
Disclosed herein are example configurations and embodiments relating to integrated RF front-end modules (FEMs), such as fully-integrated FEM'"'"'s. For example, embodiments of integrated SiGe BiCMOS FEM'"'"'s are disclosed that may enable emerging high throughput 802.11ac WLAN applications.
As discussed above, RF FEM'"'"'s are incorporated into various types of wireless devices, including computer network radios, cellular phones, PDAs, electronic gaming devices, security and monitoring systems, multi-media systems, and other electronic devices including wireless LAN (WLAN) radios. In the last decade, there have been a number of major trends in the evolution of WLAN radios. For example, with the increasing demand of higher data rate communications, the multiple-input, multiple-output (MIMO) technique has been widely adopted to increase the data rate from the 54 Mbps of a single-input single-output (SISO) operation to 108 Mbps, or more, dual stream MIMO operation. In another example, to avoid bandwidth congestion associated with the 2.4-2.5 GHz band (i.e., 2 GHz band, 2.4 GHz band, g-band), which has only 3 channels for 54 Mbps operation, dual-band (g-band and a-band) WLAN configuration has been increasingly adopted. The a-band (i.e., 5 GHz band, 5.9 Ghz band) WLAN typically operates with signals from 4.9 to 5.9 GHz, which provides an increase in the number of available channels. In yet another example, a front-end module (FEM) or front-end IC (FEIC) is typically a preferred design implementation for the radio front-end design. FEMs or FEICs not only simplify the RF design of radio front-end circuitry but also greatly reduce the layout complexity in a compact radio. For the embedded WLAN radios in portable electronic devices and MIMO radios, FEM and FEIC demonstrate the strength of integration for complicated RF circuit designs.
The emerging IEEE 802.11ac standard is a wireless computer networking standard which provides high throughput WLAN'"'"'s below 6 GHz (what is commonly referred to as the 5 GHz band). This specification may enable multi-station WLAN throughput of at least 1 Gigabit per second and a maximum single link throughput of at least 500 megabits per second (500 Mbit/s). 802.11ac chipsets are applicable in WiFi routers and consumer electronics, as well as in low-power 802.11ac technology for smartphone application processors. 802.11ac technology may provide one or more of the following technological advances, among others, over previous standards: Wider channel bandwidths (e.g., 80 MHz and 160 MHz channel bandwidths vs. 40 MHz maximum in 802.11n); more MIMO spatial streams (e.g., support for up to 8 spatial streams vs. 4 in 802.11n); multi-user MIMO, and high-density modulation (up to 256 QAM). Such advances can allow for simultaneous streaming of HD video to multiple clients throughout the home, rapid synchronization and backup of large data files, wireless display, large campus/auditorium deployments, and manufacturing floor automation, based on single-link and multi-station enhancements.
A FEM for use in a device having wireless communication functionality may comprise two or more integrated circuits, each circuit having one or more functional building blocks integrated therein and being disposed on a substrate, or die. As an example, in the context of a dual-band WiFi system, a 5 GHz power amplifier, a 2.4 GHz power amplifier, a discrete switch, and other components might be assembled onto a semiconductor die to implement the FEM system. Alternatively, two or more semiconductor die may be assembled into one FEM system, wherein the two die most likely comprise different semiconductor technologies (e.g., GaAs HBT and CMOS), wherein different technologies may each provide certain performance advantages over others. Although certain embodiments are disclosed herein in the context of 2.4 GHz and 5 GHz frequency bands, it should be understood that aspects of the present disclosure may be applicable to any suitable or feasible frequency band. For example, certain embodiments provide for integrated FEMs that operate at or near the 60 GHz radio band. Operation at higher frequencies may provide increased transmission bandwidth.
With respect to systems incorporating multiple die inside a single FEM, assembly complexity, component area, cost, package height (e.g., due to die to die bonds within the FEM, depending on the types of bonds implemented), and overall yield may be important considerations. Therefore, it may be desirable to integrate some or all of the functional building blocks of an FEM into a single semiconductor die in a manner that addresses manufacturing cost, complexity, yield, component size, and reliability issues.
Integrating multiple functional building blocks of an FEM into one semiconductor die may introduce certain complications in that some aspect of the particular semiconductor technology used may be less than optimal for one or more particular blocks. For example, an FEM utilizing a gallium-arsenide (GaAs)-based platform (e.g., GaAs HBT), which may be well suited for RF power amplification, may not have satisfactory functional characteristics for integration of low-loss, high-isolation switches. In contrast, a controller for controlling, e.g., the functional position of a switch, or which among a group of amplifier devices are enabled, might preferably, or optimally, be done in a Silicon CMOS technology platform. Generally speaking, each technology platform may import certain advantages and/or disadvantages for each building block in a given module. Moreover, it may be challenging to even identify those aspects of the semiconductor technology platform that make it less than optimal to integrate a particular building block, or blocks.
SiGe BiCMOS technology is a semiconductor technology platform that may be used to provide a platform for complete functional integration of FEM components. For example, in certain embodiments, SiGe bipolar transistor and CMOS FET technologies may be incorporated together, along with possibly other types of circuit elements, such as capacitors, resistor, interconnect metallization, etc.
One consideration that may be relevant in designing SiGe-based devices or components is the relatively low-resistivity generally associated with such substrates, which, in certain circumstances, may not provide an ideal substrate upon which to construct one or more elements of an FEM system. For example, low-resistivity substrates may interact with above-disposed technology elements to degrade the individual performance of those elements. Furthermore, in some circumstances, the low-resistivity substrate may absorb and transform RF signal energy within certain technology elements into heat or other harmonic RF signals. For example, a transmission line element above a low-resistivity substrate may be less efficient in transporting the RF signal because of loss of signal to the underlying substrate and/or dispersion effects (e.g., frequency dependent loss and phase shift). Moreover, parasitic capacitance values of the junction between the collector and substrate below and surrounding a SiGe bipolar transistor may have a dramatic impact on production of undesirable harmonic signals in connection with a desired amplified RF input signal. Likewise, a parasitic n-well-to-substrate junction used in triple-well NMOS switches may produce undesirable harmonic signals. Therefore, the identification and correlation of the impact of such parasitic substrate junctions on the production of harmonic signals, as well as the mitigation thereof using substrate engineering, may greatly affect overall performance of an FEM constructed using SiGe technology. It may therefore be desirable for integrated FEM design to address one or more of the following objectives: achieve low-loss passive matching components; achieve low NPN substrate junction capacitance (Cjs) to enhance NPN efficiency and linearity performance through effective harmonic terminating impedances; achieve low NFET Cjs to eliminate substrate loss contribution and enhance linearity by isolating and/or preventing rectification of the underlying substrate junction; and eliminate or reduce device substrate feedback through substrate isolation. As described herein, certain embodiments provide for improved performance of SiGe-based FEM'"'"'s through the use of high-resistivity layers disposed underneath, adjacent to, and/or supporting one or more SiGe BiCMOS technology elements.
As discussed herein, in accordance with certain aspects of the present disclosure, higher resistivity substrates may result in device-substrate junctions that significantly suppresses the amplitude of harmonic signals. For example, higher resistivity substrates can create junctions that have wider depletion regions and therefore lower capacitance per unit area. The modulation of such capacitances with imposed signals impinging upon the device-substrate junctions can be significantly less than with conventional ‘lower-resistivity’ substrates. Correspondingly, less modulation of the junction capacitance can result in a system in which parasitic elements attaching to various circuit devices have increased static behavior and less overall impact on signal distortion.
Certain embodiments disclosed herein provide progressively less expensive and smaller component size WiFi FEMs, while easing design challenges and providing benefits of functional integration. Functional integration of all necessary and/or desirable building blocks of an FEM onto a single SiGe BiCMOS technology platform may feature a high-resistivity substrate and may provide solutions to one or more of the concerns outlined above. The implementation, as described below, may be done in a manner that minimizes the losses of RF signals associated with, for example, both 2.4 and 5 GHz signals within the circuits, signal dispersion, and/or parasitic junction capacitances of active technology elements. The implementation of a high-resistivity layer or substrate underneath, adjacent to, and/or supporting the active semiconductor technology elements in other technologies, such as CMOS or bipolar technologies, may provide benefits similar to those generally associated with SiGe BiCMOS technology.
As is discussed in greater detail below, certain embodiments of integrated FEMs using SiGe BiCMOS technology in combination with high-resistivity bulk substrate may simplify front-end circuit design of certain 802.11 a/b/g/n/ac WLAN devices, and may provide one or more of the following improvements over certain other solutions, some of which are described in greater detail below: Incorporating functional FEM building blocks in a single die may allow for reduced cost, substrate area, package size and height, and assembly complexity; using a single semiconductor technology platform may provide for improved adjustment of input and output impedance and corresponding matching networks for the various functional blocks in a manner that reduces design challenges; reduction in the perimeter and area parasitic junction capacitances of bipolar and MOSFET transistors may reduces the magnitude of harmonic signal generated by such junctions; reduction in the losses associated with the substrate may improve insertion losses for triple well CMOS FET switches; reduction in both magnitude and frequency dependence of the RF signal losses in the substrate may allow for more predictable RF circuits to be designed with first pass success; reduction in both magnitude and frequency dependence of RF signal phase shift may allow more predictable harmonic impedance terminations to be implemented within RF amplifiers; reduction in magnitude of parasitic junctions underlying active transistors may improve AC gain at various bias points; use of high-resistivity (HR) implant (discussed in greater detail below with respect to
The RF module 120 may include transceiver circuitry. In certain embodiments, the RF module 120 comprises a plurality of transceiver circuits, such as to accommodate operation with respect to signals conforming to one or more different wireless data communication standards. Transceiver circuitry may serve as a signal source that determines or sets a mode of operation of one or more components of the RF module 120. Alternatively, or in addition, a baseband circuit 150, or one or more other components that are capable of providing one or more signals to the RF module 120 may serve as a signal source provided to the RF module 120. In certain embodiments, the RF module 120 can include a digital to analog convertor (DAC), a user interface processor, and/or an analog to digital convertor (ADC), among possibly other things.
The RF module 120 is electrically coupled to the baseband circuit 150, which processes radio functions associated with signals received and/or transmitted by one or more antennas (e.g., 95, 195). Such functions may include, for example, signal modulation, encoding, radio frequency shifting, or other function. The baseband circuit 150 may operate in conjunction with a real-time operating system in order to accommodate timing dependant functionality. In certain embodiments, the baseband circuit 150 includes, or is connected to, a central processor. For example, the baseband circuit 150 and central processor may be combined (e.g., part of a single integrated circuit), or may be separate modules or devices.
The baseband circuit 150 is connected, either directly or indirectly, to a memory module 140, which contains one or more volatile and/or non-volatile memory/data storage, devices or media. Examples of types of storage devices that may be included in the memory module 140 include Flash memory, such as NAND Flash, DDR SDRAM, Mobile DDR SRAM, or any other suitable type of memory, including magnetic media, such as a hard disk drive. Furthermore, the amount of storage included in memory module 140 may vary based on one or more conditions, factors, or design preferences. For example, memory module 140 may contain approximately 256 MB, or any other suitable amount, such as 1 GB or more. The amount of memory included in wireless device 100 may depend on factors such as, for example, cost, physical space allocation, processing speed, etc.
The wireless device 100 includes a power management module 160. The power management module 160 includes, among possibly other things, a battery or other power source. For example, power management module may include one or more lithium-ion batteries. In addition, the power management module 160 may include a controller module for management of power flow from the power source to one or more regions of the wireless device 100. Although the power management module 160 may be described herein as including a power source in addition to a power management controller, the terms “power source” and “power management,” as used herein, may refer to either power provision, power management, or both, or any other power-related device or functionality.
The wireless device 100 may include one or more audio components 170. Example components may include one or more speakers, earpieces, headset jacks, and/or other audio components. Furthermore, the audio component module 170 may include audio compression and/or decompression circuitry (i.e., “codec”). An audio codec may be included for encoding signals for transmission, storage or encryption, or for decoding for playback or editing, among possibly other things.
The wireless device 100 includes connectivity circuitry 130 comprising one or more devices for use in receipt and/or processing of data from one or more outside sources. To such end, the connectivity circuitry 130 may be connected to one or more antennas 195. For example, connectivity circuitry 130 may include one or more power amplifier devices, each of which is connected to an antenna. Antenna 195 may be used for data communication in compliance with one or more communication protocols, such as WiFi (i.e., compliant with one or more of the IEEE 802.11 family of standards) or Bluetooth, for example. Multiple antennas and/or power amplifiers may be desirable to accommodate transmission/reception of signals compliant with different wireless communications protocols. Among possibly other things, the connectivity circuitry 130 may include a Global Positioning System (GPS) receiver.
The connectivity circuitry 130 may include one or more other communication portals or devices. For example, the wireless device 100 may include physical slots, or ports, for engaging with Universal Serial Bus (USB), Mini USB, Micro USB, Secure Digital (SD), miniSD, microSD, subscriber identification module (SIM), or other types of devices through a data-communication channel.
The wireless device 100 includes one or more additional components 180. Examples of such components may include a display, such as an LCD display. The display may be a touchscreen display. Furthermore, the wireless device 100 may include a display controller, which may be separate from, or integrated with, the baseband circuit 150 and/or a separate central processor. Other example components that may be included in the wireless device 100 may include one or more cameras (e.g., cameras having 2 MP, 3.2, MP, 5 MP, or other resolution), compasses, accelerometers, or other functional devices.
The components described above in connection with
The received signal is provided from the bandpass filter to a low noise amplifier (LNA) 206, which serves to amplify the received signal. The LNA 206, which is an electronic amplifier used to amplify possibly very weak signals may be desirable in order to amplify signals captured by the antenna 295, which may be relatively weak. Although the LNA is depicted as being disposed at a point in the receiver path following the BPF 204, the LNA 206 may be disposed at any suitable position in the receiver path. The LNA 206 may be disposed following the BPF 204 in order to avoid amplification of out-of-band signals. In certain embodiments, the LNA 206 is disposed relatively close to the antenna 295 in order to reduce losses in the feedline that may otherwise reduce receiver sensitivity.
The signal may be provided from the LNA 206 to a mixer 208, and further to an analog to digital converter (ADC) 210. The mixer 208 is a nonlinear electrical circuit that converts the received RF signal to an intermediate frequency for processing by a baseband module. The mixer 208 may be configured to create new frequencies from two signals applied to it, such as the received RF signal, and a signal from a phase-locked loop (PLL) module 226, such as a signal generated by a local oscillator that operates in connection with the PLL 226. The ADC 210 may be desirable for converting the received RF signal to a digital signal for baseband processing. The digital signal may be provided by the ADC to one or more components of the wireless device via a digital control interface 228
When the switch 202 is placed in a transmit mode of operation, a path is enabled between the antenna and a transceiver portion of the RF module 220. A signal may be provided to the RF module via the digital control interface 228, such as, from a baseband processor or other module. For example, the signal may be provided to a digital to analog converter (DAC) 218, which serves to convert the received signal to an analog signal for transmission by the RF module. The converted analog signal may be passed to a mixer module 216 and further to a power amplifier module 214, which amplifies the signal to be transmitted. The power amplifier (PA) module 214 is described in further detail below with respect to
The RF module 220 may further comprise of one or more control modules 222 for controlling the operation of the various elements of the RF module. The control module 222 may comprise control functionality, such as band-selection logic, switch control logic, and/or amplifier enablement logic.
To illustrate an example PA topology, 2-stage low-band and high-band PAs are shown in
The power amplifier module 314 may comprise a plurality of signal band paths such as for two separate channels. The power amplifier module 314 may comprise any suitable number of amplifier stages. For example, the power amplifier module, or one or more portions of the power amplifier module, may contain one or more single stage and/or multi-stage power amplifiers. The power amplifier module 314 may include one or more impedance matching networks configured to match impedances between various circuit components. For example, in an embodiment comprising a multi-stage power amplifier, impedance matching circuits may be configured to match impedances between one or more transistor stages of the power amplifier. In certain embodiments, the power amplifier module comprises an impedance matching network 331A, 331B at an input portion of the power amplifier module in order to match impedances between the power amplifier module 314 and one or more circuit elements to which the power amplifier module is coupled, as well as an output impedance matching circuit 333A, 333B. In certain embodiments, the output impedance matching network 333A, 333B is configured to match the impedance of the power amplifier module 314 with impedance shown by an antenna coupled to the power amplifier module 314.
In certain embodiments, the power amplifier module 314 comprises one or more NPN bipolar transistors amplifiers formed above a high-resistivity bulk silicon substrate. Such transistor structure and formation are discussed below with respect to
In some implementations, the PA module 314 shown in
The PA module 314 may include a power amplifier controller 332 for controlling one or more power amplifiers. Although not limited as such, controlling power amplifiers generally refers to setting, modifying, or adjusting the amount of power amplification provided by the power amplifier. The PA module 314 may be a single integrated component that includes the functionality of a power amplifier controller and one or more power amplifiers. In other implementations, the wireless device 100 may include separate power amplifier control circuitry and power amplifier(s).
Typically, GaAs-based PA linearity can suffer in dynamic mode operation due to the poor thermal characteristics of the GaAs substrate. GaAs PA designs may need external circuits to improve dynamic mode linearity. In certain embodiments, more advanced bias circuitry can be implemented to resolve thermal differences between PA stages, which can result in reduced or no degradation in both linearity and gain under dynamic mode operation, while reducing the overall current requirements to operate with low EVM floors as required for 802.11ac operation. Furthermore, various other technologies may be implemented to address issues associated with GaAs designs.
A PA design can be based on silicon germanium (SiGe) BiCMOS technology, which may use, or leverage, a low impedance path to ground with through silicon vias. In certain embodiments, such a design can fit in an area of approximately 1.6×1.5 mm2. SiGe BiCMOS is a proven technology for bg-band PA design. However, there may be certain design challenges associated with realizing an amplifier with high gain and linearity at 6 GHz in SiGe technology. A challenge of producing high power at high frequency with acceptable linearity is that efficiency trends inversely with frequency due to increasing substrate losses and parasitic loading from low-resistivity silicon substrates.
As discussed above, certain conventional FEMs are configured to operate using external switches and/or diplex filters, LNAs, and PAs, wherein one or more components are separate/independent. In certain embodiments, an FEM comprises a single module, or single chip that would have all or some of these functions integrated.
In certain embodiments, various components of the FEM 400 are contained in multiple separate chips, or dies, as opposed to being fully integrated. For example, for certain high-power applications, it may be desirable to integrate some or all of the passive components of the FEM 400 into a separate chip, or Integrated Passive Device (IPD). Use of an IPD may be desirable for cost, complexity, performance, and/or other reasons. Such embodiments may include three separate dies, a first incorporating one or more power amplifiers, a second incorporating an IPD, and a third incorporating a switch and/or LNA.
Certain embodiments comprise ICs manufactured using silicon-on-insulator (SOI) technology. Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing to provide device isolation and reduce parasitic device capacitance, thereby possibly improving circuit performance. SOI-based devices differ from conventional bulk silicon-built devices in that the silicon junction is formed above and surrounded by an electrical insulator, such as silicon dioxide. In certain embodiments of SOI applications, the base substrate is a high-resistivity (e.g., approximately 1 kOhm*cm) substrate. The base substrate may have a relatively thin oxide layer disposed above it, above which another layer of silicon is disposed. Devices built on the upper silicon layer can be essentially isolated electrically and thermally from the bulk substrate and from one another. The insulating layer and top-most silicon layer may vary widely with application. SOI-based technologies may provide one or more of the following benefits relative to bulk CMOS processing: SOI CMOS built on silicon dioxide, compared with CMOS built on a bulk Si substrate, may require less-complicated well structures; latchup effects inherent in bulk CMOS circuits may be reduced or eliminated due to greater isolation of the n- and p-well structures; junction capacitance associated with source and drain regions can be significantly reduced due to the relatively thin doped Si body or well; parasitic junction capacitance beneath the source and drain regions can be significantly reduced or eliminated with the insulating oxide layer, which improves power consumption at matched performance; improvement CMOS in radiation-damage toleration may be achieved due to the relatively small volume of Si available for electron-hole pair generation by radiation.
In certain embodiments, an FEM may include an LNA and switch on a silicon-on-insulator (SOI)-type die. SOI technology may be desirable in that an SOI die provides a relatively high-resistivity substrate, and therefore, passive devices may facilitate high Q and low loss characteristics. Bipolar devices, which are well-suited for SOI-based manufacturing, are often used for LNA construction based on current/noise performance of bipolar devices. However, SOI implementation may comprise increased substrate cost compared to bulk silicon technologies. Furthermore, with respect to power amplifiers formed using SOI technology, such designs may not allow for adequate thermal dissipation characteristics.
In certain embodiments, the components of FEM 400, shown in
Although SiGe technologies have generally been built using low-resistivity bulk substrate, as described above, this low-resistivity may result in certain disadvantages that may make full FEM integration less feasible or desirable. For example, with low-resistivity, there is often feedback due to poor isolation between devices integrated on the silicon surface. Unwanted signals from one device can travel through the low-resistivity substrate to adversely affect the performance of other devices processing other signals. In certain embodiments, effects of low-resistivity substrate are attenuated or avoided by building SiGe devices on, or adjacent to, high-resistivity substrate instead. Such techniques can allow for similar design approaches to those implemented in GaAs-based technologies. As silicon wafers are often less expensive than GaAs wafers, among other advantages, using SiGe technology may provide cost benefits.
In certain device manufacturing processes, an epitaxial layer of low-resistivity substrate (e.g., n-type epitaxial layer (“n− epi”)) may be formed near a top surface of the bulk silicon substrate. For example, during processing, Arsenic, or other material from the implanted sub-collector regions may out-diffuse and redeposit on the surface of the silicon substrate, forming the low-resistivity layer. In certain embodiments, the n− epi layer may have a resistivity of around 1-100 Ohm*cm and may be approximately 1 μm in thickness. Additionally, the application of silicon dioxide on the surface of high resistivity silicon substrates, as may be used in SiGe/Si device manufacturing processes, may introduce fixed charges which attract free carriers and further decreases the bulk resistivity near the surface. Formation of such a layer at the surface may be undesirable, as its low-resistivity nature may result in unwanted parasitic current conduction leading to leakage, cross talk, high frequency losses, and susceptibility to external electric fields that induce non-linearity and harmonic distortion.
In order to at least partially alleviate potential concerns introduced by the low-resistivity layer, the wafer may be treated with a substance that at least partially damages or alters the structure of the low-resistivity layer. For example, in certain embodiments, Argon gas may be implanted in the wafer to at least partially destroy the silicon lattice in that region. Argon, being a noble gas, is inert and therefore does not react chemically with the silicon, or other material. It may not be desirable to implant lattice destroying agent and in close proximity to an active device, or any device that relies on single-crystal substrate. Therefore, in certain embodiments, the treatment of the wafer with lattice destroying agent (i.e., high-resistivity implant) is done selectively in regions at least a predetermined distance away from an active device, such as a bipolar transistor. For example, the high-resistivity implant may be implanted at least one micrometer distance from devices that would be adversely affected by the implant. In certain embodiments, the high-resistivity implant is implanted at least 10 μm from an active device. In certain embodiments, the high-resistivity implant is implanted 5-10 μm from an active device.
Various other methods of addressing parasitic conduction issues associated with low-resistivity may be used in place of, or in addition to, the high-resistivity implant discussed above. For example, in certain embodiments, the wafer may be treated with a layer of polysilicon or amorphous silicon prior to oxide application (i.e., a “trap-rich” layer), which is configured to lock the free carriers up, thereby inhibiting mobility at operating frequencies. Such a method may be suitable for SOI applications, and may be capable of withstanding high temperature conditions needed for CMOS processing. In addition, any other suitable or desirable mechanism for restoring high-resistivity characteristics of the wafer may advantageously be utilized in connection with embodiments disclosed herein. Furthermore, one or more trenches, as shown, may be etched into the wafer, thereby impeding the movement of carriers in the substrate across the trench(es).
Although high-resistivity substrate may be conducive to desirable bipolar transistor construction, it may be desirable for certain devices, such as CMOS, to be associated with low-resistivity substrate. Therefore, in certain embodiments, one or more devices, such as CMOS FET devices and/or SiGe bipolar HBT devices, are grown on a bulk silicon substrate. Due to undesirable effects of high-resistivity substrate on certain devices, low-resistivity substrate (e.g., p-type implant (“p well”)) may be implanted beneath, or adjacent to, such devices. Therefore, the transistor 520 may benefit from low resistivity p-well diffusion and contact to the substrate, as well as a surrounding high-resistivity region (discussed in greater detail below). The p well may comprise a band that at least partially surrounds the collector of the transistor 520B, or may be a local diffusion area close to the collector. Although certain embodiments of transistors and substrates are described herein in the context of NPN, NFET, or other impurity-type devices, it should be understood that any of the embodiments disclosed herein may comprise n-type or p-type collector, well, and bulk substrates. As a p-well band, there may be one or more certain critical distances from the n-well that minimizes or substantially reduces NPN collector-junction capacitance and harmonic generation. In certain embodiments, without a band of p-well, the collector n-well would not be adequately isolated from the n-epi layer that is grown on top of the high resistivity substrate unless the isolation is achieved by rendering the n-epi layer to high resistivity by some implant or counter doping or deep trench.
In certain embodiments, a pocket of charge may collect in a region between the trench and p well shown in
In certain embodiments, the p well may be disposed between the transistor 520B and one or more passive or active devices disposed on the substrate. Therefore, the p well may provide at least partial electrical isolation between the transistor 520B and such devices.
As shown in
Low-resistivity implant disposed too closely to an active device may lead to various issues, such as undesirable capacitive coupling between the device and the low-resistivity region. For example, when low-resistivity substrate is too close to an active device, a junction capacitance may be formed between an n-type layer of the device and a p-type low-resistivity implant. Such issues may at least partially defeat the purpose of utilizing high-resistivity substrate to begin with. Therefore, in certain embodiments, an RF device 556 is disposed above and immediately adjacent to high-resistivity substrate 501B.
In order to achieve some of the benefits associated with low-resistivity, a low-resistivity implant 551B may be implanted in the vicinity of, though not too close to, the device 556. In certain embodiments, in order to avoid undesirable coupling or other results, the low-resistivity implant 551 does not encroach within a predetermined distance of the device, or within a predetermined distance of a buried layer of the device. With respect to various regions of the device 556, the distance between the device and the low-resistivity layer 551B may be greater than approximately one micrometer. Certain embodiments disclosed herein may provide for at least partially optimized placement of low-resistivity implant. For example, in certain embodiments, low-resistivity implant 551B is disposed at a distance far enough from the device 556 to avoid substantial coupling (e.g., 1 μm away), but close enough to make efficient use of space (e.g., within 10-15 μm of the device).
As described above, it may be desirable in embodiments utilizing a low-resistivity region (e.g., p well) such as that shown in
The space between the RF device and the low-resistivity region may be inhabited at an upper surface of the substrate by a low-resistivity epitaxial layer, as described above in connection with
Passive elements, such as resistors, capacitors, inductors, and transmission lines, may be disposed directly above high-resistivity regions. Although such high-resistivity regions, as described above, comprise substrate in which an upper layer of the crystal lattice has been destroyed, such passive components do not require such upper lattice, and may experience improved high frequency performance in the presence of the high-resistivity region.
With a low resistivity substrate p-well diffusion and contact provided a certain distance from the device 502G, and a surrounding high resistivity region that has been rendered high resistivity by some implant or counter doping or deep trench, the transistor 502G may achieve substantial electrical isolation from neighboring devices. For example, the substrate may have disposed thereon one or more other passive or active devices, wherein the p well is disposed at least partially between the transistor 502G and such devices. With respect to other passive devices (e.g., inductors fashioned in the metal layers subsequent to the formation of the FET device), such devices may have higher performance as a result of being disposed directly above the high resistivity region, wherein the high-resistivity region has been rendered high resistivity by high-resistivity implant or counter doping or utilization of one or more deep trenches. The transistor device 502G may be part of an RF switch circuit, or may form part of a mixer circuit or low noise amplifier circuit, or other circuit module.
The RF devices formed on high-resistivity bulk substrate, as disclosed herein, may be formed using traditional silicon technologies, or may be formed using SiGe/Si BiCMOS technology. One advantage of SiGe BiCMOS technology is relatively easy integration of RF core and analog circuits. In certain embodiments, RF core components may be based on SiGe transistors and analog components, such as bias circuits, power amplifiers, low noise amplifiers, RF switches, and power detectors. By allowing for integration of CMOS logic with heterojunction bipolar transistors, SiGe can be particularly suitable for mixed-signal circuits. Heterojunction bipolar transistors have higher forward gain and lower reverse gain than traditional homojunction bipolar transistors. This translates into better low-current and high-frequency performance. Being a heterojunction technology with an adjustable band gap, SiGe may provide more flexible band gap tuning than silicon-only technology.
Power amplifiers may have improved thermal characteristics in SiGe-based applications when compared to SOI-based applications. For example, in SOI-based applications, the insulator that exists between the silicon and the active device may have low thermal conductivity, at least partially preventing dissipation of heat generated by the PA device. A SiGe-based transistor may be built on the semi-insulating substrate, allowing heat to be removed via the substrate, as in other silicon-based applications. Furthermore, by providing the ability to integrate CMOS and bipolar technologies, SiGe applications may provide improved linearity.
SiGe applications may be built on high-resistivity bulk silicon substrate having n-type diffusions. Higher resistivity may improve the transistor-level performance, and allow for integration of, for example, high-Q passive components, filters, switches, and amplifiers on a single chip. Performance of passive components associated with an FEM built on high-resistivity substrate may depend largely on the type of back-end metals used in connection with the substrate.
As discussed above, traditional SiGe technology incorporates bulk silicon having relatively low resistivity, such as around 10-50 Ohm*cm. Certain preferred embodiments described herein, conversely, involve providing a high-resistivity substrate on which transistors and/or other devices are built using a modified or identical process flow. Integration of an FEM using high-resistivity BiCMOS SiGe technology may provide certain advantages over other technologies, such as the ability to integrate both the switch and the PA transistors into the bulk substrate. For example, transistor junction capacitance (Cjs) may be substantially reduced, such as by a factor of 10 or more, in high-resistivity applications. In addition, the Cjs series resistive component associated with the bulk substratemay be increased by up to 10-100 times or more compared to that obtained with low resistivity substrate. As a result, power loss may be substantially reduced. Low parasitic contribution from the bulk substrate may provide, among other things, improved RF isolation between neighboring circuits and/or neighboring devices, and lower losses due to the underlying low-loss silicon region. Low parasitic contribution from the bulk will further alleviate the otherwise constrained impedance tuning necessary to optimally match power amplifier stages harmonic frequencies for linear or saturated power amplifier applications.
Various challenges can arise when converting the underlying substrate from low to high resistivity. For example, when the bulk substrate resistivity is changed, depletion widths associated with active components disposed on n-type diffusions tend to be larger than in low-resistivity substrates. Such increase in depletion width may be significant, such as by one or more orders of magnitude. Large depletion widths may pose certain problems, such as allowing RF or DC signals to interfere to neighboring devices, or possibly to the back of the wafer.
As illustrated above in connection with
At block 630, one or more active devices are formed on the substrate. Examples of such devices may include transistors of various types. One or more passive devices (resistors, inductors, etc.) may be formed on the substrate at block 650. Passive devices may be advantageously formed above regions of the substrate where the surface has been treated to return the substrate to high-resistivity at or near its surface. In certain embodiments, the process 600 allows for integration of RF devices, such as power amplifiers, on high-resistivity silicon substrate.
As described above, during manufacturing process of high-resistivity silicon wafers, an epitaxial layer of relatively low-resistivity silicon may form on an upper surface of the wafer. Therefore, the process 600 may include a step 640 that involves destroying at least a portion of the low-resistivity epitaxial layer in selected regions to restore high-resistivity characteristics of the substrate in those regions. This step is illustrated at block 640, and may be performed by treating the surface of the substrate with Argon gas, thereby at least partially destroying the crystal lattice in that region.
The front-end module 700B shown in
As shown in
In certain embodiments, a FEM may comprise dual band architecture.
The FEM 900 includes an antenna port 995 that is coupled to a switch having four positions. Two of the positions of the antenna correspond to receiver paths of the front-end module, one for the 2.4 GHz band, and another for the 5 GHz band. The remaining two positions of the switch correspond to transmitter paths of the FEM 900, one for each of the relevant bands, similarly to the receiver portion. The FEM 900 comprises a two-stage power amplifier 914A in connection with the g-band mode of operation and a three stage amplifier 914B in connection with the a-band mode of operation. Each band of the transmitter portion may include one or more matched filters for matching impedance between the power amplifiers and, for example, the antenna, or other components of a wireless device. The FEM 900 further includes a control logic module 922 for controlling one or more elements of the front-end module, such as the switch 902.
The FEM 900 includes a detector module 924 for detecting a signal on one or more lines of the transmitter portion to provide data for use in output power regulation. In connection with the detector module 924, the FEM 900 may include one or more couplers (925A, 925B), such as directional couplers, or other types of couplers. The couplers 925A, 925B enable power coupling between the transmitter portion and the detector module 924. In some implementations, power detection can be realized at an inter-stage matching circuit between a driver and output stage. Power detection at an intermediate stage may be generally proportional to the actual output power. Furthermore, by coupling to the transmitter portion at a position other than the output of the amplifier may advantageously provide at least partial isolation from antenna mismatch, such that power-reading stability is improved.
Embodiments of front-end modules disclosed herein may be configured to conform to band gain and rejection specifications of one or more wireless communication standards, such as 802.11ac (see
Satisfactory gain/rejection characteristics may be difficult to achieve in 2-stage SiGe implementations using low-resistivity bulk substrate due to intrinsically higher insertion loss of corresponding filter implementations. However, in certain embodiments, 3-stage SiGe amplifiers may used with 6-th order elliptical filtering to achieve adequate performance. Three stages may be required, as opposed to two, due to increases in loss from higher-order filtering and low-resistivity bulk silicon substrate. Therefore, with respect to low-resistivity SiGe-based technologies, it may be desirable to implement coexistence filtering using a sixth-order elliptical filter, in order to meet 802.11ac specifications.
However, high-resistivity SiGe solutions, as described herein, may allow for 802.11ac compliant FEMs to utilize 2-stage solutions that are comparable to 2-stage GaAs performance. Such 2-stage solutions may advantageously provide satisfactory performance without the additional increases in current consumption, physical size, and overall increase in circuit complexity that may be required to accommodate a 6th order filter, like that shown in
With respect to
While various embodiments of integrated front-end modules have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible. For example, embodiments of integrated FEMs are applicable to different types of wireless communication devices, incorporating various FEM components. In addition, embodiments of integrated FEMs are applicable to systems where compact, high-performance design is desired. Some of the embodiments described herein can be utilized in connection with wireless devices such as mobile phones. However, one or more features described herein can be used for any other systems or apparatus that utilize of RF signals.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.
The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.
While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.