VERTICALLY STACKED NFETS AND PFETS WITH GATE-ALL-AROUND STRUCTURE

• US 20190319095A1
• Filed: 06/21/2019
• Published: 10/17/2019
• Est. Priority Date: 11/02/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Jingyun, Ando, Takashi, Hashemi, Pouya, Lee, Choonghyun, Reznicek, Alexander
• Granted Patent: US 10,879,352 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 : oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 : using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a vertical stack of a first nanosheet stack of alternating nanosheets of a sacrificial semiconductor nanosheet and a semiconductor channel material nanosheet, and a second nanosheet stack of alternating nanosheets of a sacrificial semiconductor nanosheet and a semiconductor channel material nanosheet, wherein the vertical stack is present above a semiconductor substrate and beneath a sacrificial gate structure and a dielectric spacer;

recessing each sacrificial semiconductor nanosheet of the first and second nanosheet stacks;

forming a pFET S/D SiGe region having a first germanium content on physically exposed sidewalls of each semiconductor channel material nanosheet of the first nanosheet stack;

forming a germanium oxide layer on at least physically exposed surfaces of each pFET S/D SiGe region;

performing a condensation anneal to convert an upper portion of each pFET S/D SiGe region into a SiGe region having a second germanium content that is greater than the first germanium content, wherein the germanium oxide layer located on each pFET S/D SiGe region is simultaneously converted into a silicon dioxide layer;

forming an nFET S/D region on physically exposed sidewalls of each Si channel material nanosheet of the second nanosheet stack and on the silicon dioxide layer;

removing the sacrificial gate structure and each recessed sacrificial semiconductor nanosheet of the first and second nanosheet stacks to suspend each semiconductor channel material nanosheet and to provide a gate cavity; and

forming a first functional gate structure in the gate cavity and on physically exposed surfaces of each suspended semiconductor channel material nanosheet of the first nanosheet stack, and forming second functional gate structure in the gate cavity and on physically exposed surfaces of each suspended semiconductor channel material nanosheet of the second nanosheet stack.

2. The method of claim 1, further comprising forming an inner spacer on physically exposed sidewalls of each recessed sacrificial semiconductor nanosheet prior to the forming the pFET S/D SiGe region.

3. The method of claim 1, wherein the first and second functional gate structures each comprises a same work function metal.

4. The method of claim 1, wherein the first functional gate structure comprises a p-type work function metal and the second functional gate structure comprises an nFET functional gate structure.

5. The method of claim 1, wherein the condensation anneal is performed at a temperature of less than 800°

C. and in an inert ambient.

6. The method of claim 1, further comprising forming a dielectric isolation layer on a surface of the semiconductor substrate and beneath the vertical stack of first and second nanosheet stacks prior to forming the nFET S/D SiGe regions.

7. The method of claim 1, further comprising forming a shared S/D contact structure on a first side of the suspended semiconductor channel material nanosheets.

8. The method of claim 7, further comprising forming an nFET S/D contact structure and a pFET S/D contact structure located on a second side of the suspended semiconductor channel material nanosheets, opposite the first side, wherein the nFET S/D contact is present in the nFET S/D region and the pFET contact structure is present in the SiGe region and the pFET S/D SiGe region.

9. The method of claim 1, wherein the forming of the pFET S/D SiGe region comprises an epitaxial growth process.

10. The method of claim 1, wherein the first germanium content is from 50 atomic percent to 60 atomic percent.

11. The method of claim 10, wherein the second germanium content is from 55 atomic percent to 75 atomic percent.

12. The method of claim 1, wherein each sacrificial semiconductor nanosheet of the first nanosheet stack and the second nanosheet is composed of a first semiconductor material that is resistant to Ge condensation.

13. The method of claim 12, wherein the first semiconductor material that provides each wherein each sacrificial semiconductor nanosheet of the first nanosheet stack and the second nanosheet is composed of a silicon germanium alloy having a germanium content of less than 50 atomic percent.

14. The method of claim 12, wherein each semiconductor channel material nanosheet of the first nanosheet stack and the second nanosheet is composed of a second semiconductor material that has a different etch rate than the first semiconductor material and is resistant to Ge condensation.

15. The method of claim 14, wherein the second semiconductor material is composed of a silicon germanium alloy having a germanium content of less than 50 atomic percent and the second semiconductor material differs from the first semiconductor material.

16. The method of claim 1, wherein the recessing of each sacrificial semiconductor nanosheet of the first and second nanosheet stacks comprises a lateral etching process.

17. The method of claim 1, wherein the forming of the nFET S/D region comprises an epitaxial growth process.

18. The method of claim 1, wherein the nFET S/D region has a height that is above a topmost surface of a topmost semiconductor channel material nanosheet of the second nanosheet stack.

19. The method of claim 1, wherein the nFET S/D region has a height that is coplanar with a topmost surface of a topmost semiconductor channel material nanosheet of the second nanosheet stack.

20. The method of claim 1, wherein the nFET S/D region has a height that is beneath a topmost surface of a topmost semiconductor channel material nanosheet of the second nanosheet stack, but not lower than the bottommost surface of the topmost semiconductor channel material nanosheet of the second nanosheet stack