Supportive Layer in Source/Drains of FinFET Devices

• US 20190319098A1
• Filed: 04/13/2018
• Published: 10/17/2019
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TAI, Roger, LI, Chii-Horng, JENG, Pei-Ren, LEE, Yen-Ru, LIN, Yan-Ting, CHIN, Chih-Yun
• Granted Patent: US 10,854,715 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

Claims

1. A semiconductor structure comprising:

a fin on a substrate;

a gate structure over the fin; and

a source/drain in the fin proximate the gate structure, the source/drain comprising;

a bottom layer,

a supportive layer over the bottom layer, and

a top layer over the supportive layer, wherein the supportive layer has a different property than the bottom layer and the top layer, the different property selected from a group consisting of a different material, a different natural lattice constant, a different dopant concentration, and a different alloy percent content.

2. The semiconductor structure of claim 1, wherein the supportive layer comprises a material selected from a group consisting of silicon, silicon germanium, boron doped silicon germanium, phosphorus doped silicon, phosphorus doped silicon germanium, arsenic doped silicon, and arsenic doped silicon germanium.

3. The semiconductor structure of claim 1, wherein the bottom layer has a thickness in a range from about 30 nm to about 50 nm and the top layer has a thickness in a range from about 15 nm to about 45 nm.

4. The semiconductor structure of claim 1, wherein the fin comprises silicon germanium.

5. The semiconductor structure of claim 1, wherein the bottom layer of the source/drain comprises p-doped silicon germanium having a first germanium atomic percent content and wherein the top layer comprises p-doped silicon germanium having a second germanium atomic percent content greater than the first germanium atomic percent content.

6. The semiconductor structure of claim 1, wherein the source/drain is a merged source/drain.

7. The semiconductor structure of claim 1, wherein the source/drain is unmerged with another source/drain in another fin.

8. The semiconductor structure of claim 1, wherein the source/drain is partially merged.

9. The semiconductor structure of claim 1, wherein the supportive layer comprises silicon germanium with a germanium atomic percent content in a range from 1% to 50%.

10. The semiconductor structure of claim 1, wherein the supportive layer further comprises a p-type dopant of boron in a concentration in a range from 5×

10¹⁹ cm<sup>−

3</sup> to 10²¹ cm<sup>−

3</sup>.

11. The semiconductor structure of claim 5, wherein the supportive layer comprises silicon germanium having a germanium atomic percent content less than the first germanium atomic percent content of the bottom layer and less than the second germanium atomic percent content of the top layer.

12-16. -16. (canceled)

17. A semiconductor structure comprising:

a substrate;

a fin on the substrate;

a gate structure over the fin; and

source/drains in the fin on opposing sides of the gate structure, each of the source/drains comprising;

a bottom layer,

a plurality of supportive layers over the bottom layer,

one or more intermediate layers between the plurality of supportive layers; and

a top layer over the plurality of supportive layers, wherein the plurality of supportive layers comprises silicon germanium with an atomic percent content of germanium less than the bottom layers, less than the one or more intermediate layers, and less than the top layer.

18. The semiconductor structure of claim 17, wherein the plurality of supportive layers number in a range from two layers to twenty layers.

19. The semiconductor structure of claim 17, wherein the bottom layer, the one or more intermediate layers, and the top layer comprise p-doped silicon germanium.

20. The semiconductor structure of claim 17, wherein each of the supportive layers has a thickness in a range from about 0.5 nm to about 4 nm.

21. A semiconductor structure comprising:

a fin on a substrate;

a gate structure over the fin; and

a source/drain in the fin proximate the gate structure, the source/drain comprising;

a bottom layer comprising p-doped silicon germanium having a first germanium atomic percent content,

a supportive layer over the bottom layer, and

a top layer over the supportive layer, the top layer comprising p-doped silicon germanium having a second germanium atomic percent content greater than the first germanium atomic percent content, wherein the supportive layer comprises silicon germanium having a third germanium atomic percent content less than the first germanium atomic percent content of the bottom layer and less than the second germanium atomic percent content of the top layer.

22. The semiconductor structure of claim 21, wherein the fin comprises silicon germanium having a fourth germanium atomic percent content less than the third germanium atomic percent content of the supportive layer.

23. The semiconductor structure of claim 21, wherein the source/drain induces strain to a channel defined by the gate structure over the fin.

24. The semiconductor structure of claim 21, wherein the source/drain is a merged source/drain.

25. The semiconductor structure of claim 21, wherein the supportive layer comprises silicon germanium with a germanium atomic percent content in a range from 1% to 50%.