NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A DEUTERATED LAYER IN A MULTI-LAYER CHARGE-TRAPPING REGION
First Claim
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1. A charge trap memory device, comprising:
- a substrate having a source region, a drain region, and a channel region electrically connecting the source region and drain region;
a tunnel dielectric layer disposed above the substrate over the channel region; and
a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer
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Abstract
Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed
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Citations
20 Claims
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1. A charge trap memory device, comprising:
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a substrate having a source region, a drain region, and a channel region electrically connecting the source region and drain region; a tunnel dielectric layer disposed above the substrate over the channel region; and a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first nitride layer - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A charge trap memory device, comprising:
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a substrate having a source region, a drain region, and a channel region formed from a thin film of semiconducting material overlying a surface on the substrate and electrically connecting the source and drain; a tunnel dielectric layer disposed above the substrate over the channel region; and a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer disposed above the first layer. - View Dependent Claims (10, 11, 12, 13)
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14. A charge trap memory device comprising:
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a vertical channel formed from a projection of semiconducting material extending from a first diffusion region formed on a surface on a substrate to a second diffusion region formed over the surface of the substrate, the vertical channel electrically connecting the first diffusion region to the second diffusion region; a tunnel dielectric layer abutting the vertical channel; a multi-layer charge-trapping region including a first deuterated layer abutting the tunnel dielectric layer, a first nitride layer comprising an oxygen-rich nitride abutting the first deuterated layer, and a second nitride layer comprising a silicon-rich, oxygen-lean nitride overlying the first nitride layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification