FORMATION OF SELF-ALIGNED BOTTOM SPACER FOR VERTICAL TRANSISTORS

• US 20190319114A1
• Filed: 06/27/2019
• Published: 10/17/2019
• Est. Priority Date: 12/20/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BAO, RUQIANG, JAGANNATHAN, HEMANTH, LEE, CHOONGHYUN, MOCHIZUKI, SHOGO
• Granted Patent: US 10,749,012 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

Claims

1. A semiconductor device comprising:

a source/drain region; and

a bottom gate spacer arranged on the source/drain region, the bottom gate spacer comprising a silicon germanium layer and a silicon oxynitride layer.

2. The semiconductor device of claim 1, wherein the silicon germanium layer comprises from about 40 to about 80 atomic percentage (%) germanium.

3. The semiconductor device of claim 1, wherein the silicon germanium layer comprises from about 20 to about 60 atomic percentage (%) germanium.

4. The semiconductor device of claim 2 further comprising a germanium containing layer arranged on sidewalls of a fin.

5. The semiconductor device of claim 3 further comprising a germanium containing layer arranged on sidewalls of a fin.

6. The semiconductor device of claim 4, wherein the germanium containing layer comprises germanium oxynitride.

7. The semiconductor device of claim 5, wherein the germanium containing layer comprises germanium oxynitride.

8. The semiconductor device of claim 4, wherein the germanium containing layer comprises germanium oxide.

9. The semiconductor device of claim 5, wherein the germanium containing layer comprises germanium oxide.

10. The semiconductor device of claim 1 further comprising forming a metal gate on the bottom gate spacer.

11. A semiconductor device comprising:

a source/drain region; and

a bottom gate spacer comprising a silicon oxide layer and a silicon germanium layer arranged on the source/drain region.

12. The semiconductor device of claim 11, wherein the silicon germanium layer comprises from about 40 to about 80 atomic percentage (%) germanium.

13. The semiconductor device of claim 11, wherein the silicon germanium layer comprises from about 20 to about 60 atomic percentage (%) germanium.

14. The semiconductor device of claim 12 further comprising a germanium containing layer arranged on sidewalls of a fin.

15. The semiconductor device of claim 13 further comprising a germanium containing layer arranged on sidewalls of a fin.

16. The semiconductor device of claim 14, wherein the germanium containing layer comprises germanium oxynitride.

17. The semiconductor device of claim 15, wherein the germanium containing layer comprises germanium oxynitride.

18. The semiconductor device of claim 14, wherein the germanium containing layer comprises germanium oxide.

19. The semiconductor device of claim 15, wherein the germanium containing layer comprises germanium oxide.

20. The semiconductor device of claim 11 further comprising forming a metal gate on the bottom gate spacer.