SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURINGTHE SAME

• US 20190319337A1
• Filed: 04/11/2018
• Published: 10/17/2019
• Est. Priority Date: 04/11/2018
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: YEN, Han-Chee
• Granted Patent: US 10,811,763 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/14 characterised by the material or its electrical properties printed circuit boards H05K1/00
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/38 : formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/48 : Earthing means; Earth screens; Counterpoises
• CPC Class Codes: H01Q 15/14 : Reflecting surfaces; Equivalent structures electromagnetic shields H01Q1/526
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40
• CPC Class Codes: H01Q 9/0414 : in a stacked or folded configuration
• CPC Class Codes: H01Q 9/30 : with feed to end of elongated active element, e.g. unipole H01Q9/44 takes precedence
• CPC Class Codes: H05K 1/0213 : Electrical arrangements not otherwise provided for

Abstract

A semiconductor device package includes a circuit layer, an antenna structure, a first encapsulant and a reflector. The circuit layer has a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface. The antenna structure is disposed within the circuit layer. The first encapsulant is disposed on the first surface of the circuit layer, the first encapsulant having a surface. The reflector is disposed on the first encapsulant. The third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

Claims

1. A semiconductor device package, comprising:

a circuit layer having a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface;

an antenna structure disposed within the circuit layer;

a first encapsulant disposed on the first surface of the circuit layer, the first encapsulant having a surface; and

a reflector disposed on the first encapsulant,

wherein the third surface of the circuit layer is substantially coplanar with the surface of the first encapsulant.

2. The semiconductor device package of claim 1, further comprising

a second encapsulant disposed on the second surface of the circuit layer, the second encapsulant having a first surface, a second surface opposite to the first surface of the second encapsulant and a third surface extended between the first surface of the second encapsulant and the second surface of the second encapsulant;

and

a conductive layer disposed on the first surface of the second encapsulant.

3. The semiconductor device package of claim 2, wherein

the conductive layer includes a first portion at a position corresponding to the antenna structure and a second portion separated from the first portion, and

the second portion of the conductive layer extends from the first surface of the second encapsulant to the third surface of the second encapsulant, the third surface of the circuit layer and the surface of the first encapsulant.

4. The semiconductor device package of claim 3, wherein the second portion of the conductive layer is in contact with the reflector.

5. The semiconductor device package of claim 1, further comprising an electrical contact disposed adjacent to the first surface of the circuit layer, wherein a portion of the electrical contact is exposed from the first encapsulant and is in contact with the reflector.

6. The semiconductor device package of claim 1, wherein the reflector is grounded and disposed at a position corresponding to the antenna structure.

7. A semiconductor device package, comprising:

a circuit layer having a first surface, a second surface opposite to the first surface and a third surface extended between the first surface and the second surface;

a reflector disposed within the circuit layer;

a first encapsulant disposed on the first surface of the circuit layer; and

an antenna structure disposed on the first encapsulant.

8. The semiconductor device package of claim 7, wherein the reflector defines a slot at a position corresponding to the antenna structure.

9. The semiconductor device package of claim 8, further comprising an electronic component disposed on the second surface of the circuit layer, wherein the circuit layer includes a feeding line disposed adjacent to the second surface of the circuit layer and electrically connected to the electronic component, and wherein the feeding line is disposed at a position corresponding to the slot of the reflector.

10. The semiconductor device package of claim 9, further comprising a conductive layer disposed on the first encapsulant and separated from the antenna structure.

11. The semiconductor device package of claim 10, wherein the first encapsulant has a first surface and a second surface, and the conductive layer is extended from the first surface of the first encapsulant to the second surface of the first encapsulant and the third surface of the circuit layer.

12. The semiconductor device package of claim 11, wherein a portion of the reflector is exposed from the third surface of the circuit layer and is in contact with the conductive layer.

13. The semiconductor device package of claim 11, further comprising a second encapsulant disposed on the second surface of the circuit layer and encapsulating the electronic component, wherein the conductive layer is extended to a surface of the second encapsulant.

14. The semiconductor device package of claim 7, further comprising:

a second encapsulant disposed on the first encapsulant and encapsulating the antenna structure; and

a conductive layer disposed on the second encapsulant.

15. The semiconductor device package of claim 14, wherein

the conductive layer includes a first portion at a position corresponding to the antenna structure and a second portion separated from the first portion,

the second encapsulant has a first surface and a second surface, and

the second portion of the conductive layer is extended from the first surface of the second encapsulant to the second surface of the second encapsulant, a surface of the first encapsulant and the third surface of the circuit layer.

16. A semiconductor device package, comprising:

a reflector;

a first encapsulant disposed on the reflector; and

an antenna structure disposed on the first encapsulant,

wherein a tolerance of a distance between the antenna structure and the reflector is about 2 μ

m to about 8 μ

m.

17. The semiconductor device package of claim 16, further comprising a circuit layer having a first surface, a second surface opposite to the first surface and a third surface extended between the first surface of the circuit layer and the second surface of the circuit layer, wherein the antenna structure is disposed within the circuit layer, and the first encapsulant covers the first surface of the circuit layer and separates the antenna structure from the reflector.

18. The semiconductor device package of claim 17, further comprising:

a second encapsulant covering the second surface of the circuit layer; and

a conductive layer disposed on the second encapsulant.

19. The semiconductor device package of claim 18, wherein

the conductive layer includes a first portion at a position corresponding to the antenna structure and a second portion separated from the first portion,

the second encapsulant has a first surface and a second surface, and

the second portion of the conductive layer is extended from the first surface of the second encapsulant to the second surface of the second encapsulant, the third surface of the circuit layer and a surface of the first encapsulant.

20. The semiconductor device package of claim 16, further comprising a circuit layer having a first surface and a second surface opposite to the first surface, wherein the reflector is disposed within the circuit layer, and the first encapsulant covers the first surface of the circuit layer and separates the antenna structure from the reflector.

21. The semiconductor device package of claim 20, wherein the reflector defines a slot at a position corresponding to the antenna structure.

22. The semiconductor device package of claim 21, further comprising an electronic component disposed on the second surface of the circuit layer, wherein the circuit layer includes a feeding line adjacent to the second surface of the circuit layer and electrically connected to the electronic component, and the feeding line is disposed at a position corresponding to the slot of the reflector.

23-28. -28. (canceled)