INTEGRATED ANTENNA ARRAY PACKAGING STRUCTURES AND METHODS

• US 20190319338A1
• Filed: 04/13/2018
• Published: 10/17/2019
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gu, Xiaoxiong, Liu, Duixian, Baks, Christian W., Valdes Garcia, Alberto
• Granted Patent: US 11,189,905 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32235 the layer connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15323 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/1904 : Component type
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/0087 : Apparatus or processes specially adapted for manufacturing antenna arrays manufacturing waveguides H01P11/00
• CPC Class Codes: H01Q 21/061 : Two dimensional planar arrays
• CPC Class Codes: H01Q 21/065 : Patch antenna array

Abstract

An apparatus includes an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element. The antenna array package also includes an array of sub-pattern interface packages mated to the mating surface of the antenna array package cover. Each sub-pattern interface package of the array of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit electrically and mechanically coupled to the package carrier, and a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package. Methods for mounting the above apparatus into a host circuit are also disclosed herein.

Claims

1. An apparatus comprising:

an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element;

an array of sub-pattern interface packages mated to the mating surface of the antenna array package cover; and

wherein each sub-pattern interface package of the array of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit electrically and mechanically coupled to the package carrier, and a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package.

2. The apparatus of claim 1, wherein each sub-pattern interface package of the array of sub-pattern interface packages is disposed below a corresponding antenna array sub-pattern of the array of antenna array sub-patterns.

3. The apparatus of claim 1, wherein the sub-pattern integrated circuit is flip-chip bonded to the package carrier.

4. The apparatus of claim 1, wherein the antenna array package cover and the array of sub-pattern interface packages form an antenna array package.

5. The apparatus of claim 4, wherein the antenna array package is mounted on a host circuit.

6. The apparatus of claim 5, wherein the antenna array package is mounted on the host circuit via a ball grid array (BGA) or a land grid array (LGA) socket.

7. The apparatus of claim 5, wherein the host circuit comprises one or more heat sinks that are thermally connected to the plurality of sub-pattern integrated circuits via a plurality of thermal conduits.

8. The apparatus of claim 7, wherein a thermal conduit of the one or more thermal conduits comprises a pedestal.

9. The apparatus of claim 5, further comprising a spacer frame disposed between the antenna array package cover and the host circuit.

10. The apparatus of claim 1, wherein the antenna array package cover comprises a set of antenna feeds for each antenna array sub-pattern of the array of antenna array sub-patterns.

11. The apparatus of claim 1, wherein the antenna array package cover comprises a test interface element that is electrically connected to at least one sub-pattern integrated circuit.

12. The apparatus of claim 1, wherein the array of sub-pattern interface packages are secured to the mating surface of the antenna array package cover via one or more of supporting balls, an adhesive, and at least one fastener.

13. The apparatus of claim 1, wherein the antenna array package cover or the package carrier comprises multiple layers.

14. The apparatus of claim 1, wherein the package carrier comprises bonding pads for a solder ball grid array.

15. The apparatus of claim 1, wherein each antenna element comprises a patch of conductive material disposed on or below the radiating surface.

16. The apparatus of claim 1, wherein the antenna elements are disposed on multiple layers of the antenna array package cover.

17. A method comprising:

providing an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element;

providing a plurality of sub-pattern interface packages wherein each sub-pattern interface package of the plurality of sub-pattern interface packages comprises a package carrier and a sub-pattern integrated circuit bonded to bonding pads of the package carrier;

mating the plurality of sub-pattern interface packages to the mating surface of the antenna array package cover to produce an antenna array package; and

mounting the antenna array package onto a host circuit.

18. The method of claim 17, wherein each sub-pattern interface package of the plurality of sub-pattern interface packages is disposed below a corresponding antenna array sub-pattern of the array of antenna array sub-patterns provided by the antenna array package cover and wherein each sub-pattern interface package of the plurality of sub-pattern interface packages comprises a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package.

19. A method comprising:

providing an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element;

providing a plurality of sub-pattern interface packages wherein each sub-pattern interface package of the plurality of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit bonded to bonding pads of the package carrier;

mounting the plurality of sub-pattern interface packages onto a host circuit; and

mating the plurality of sub-pattern interface packages to the mating surface of the antenna array package cover subsequent to mounting the plurality of sub-pattern interface packages onto the host circuit.

20. The method of claim 19, wherein each sub-pattern interface package of the plurality of sub-pattern interface packages is disposed below a corresponding antenna array sub-pattern of the array of antenna array sub-patterns provided by the antenna array package cover and wherein each sub-pattern interface package of the plurality of sub-pattern interface packages comprises a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package.