FAST OVERVOLTAGE PROTECTION CIRCUIT WITH DIGITAL CONTROL
1. An apparatus comprising:
- a receiver including a signal detection circuit;
a transmitter; and
a control circuit configured to receive an overvoltage signal from the receiver and to disable an output of the transmitter based on the overvoltage signal,wherein;
the signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, andthe control circuit is configured to disable the output of the transmitter for a programmable time period.
A wired communication apparatus includes a receiver, a transmitter and a control circuit. The receiver includes a signal detection circuit. The transmitter includes a number of digital-to-analog converter (DAC) cells. The control circuit can receive an overvoltage signal from the receiver and can disable an output of the transmitter based on the overvoltage signal. The signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit can disable the output of the transmitter for a programmable time period.
- 1. An apparatus comprising:
a receiver including a signal detection circuit; a transmitter; and a control circuit configured to receive an overvoltage signal from the receiver and to disable an output of the transmitter based on the overvoltage signal, wherein; the signal detection circuit is operable in a special mode to detect an overvoltage event at an input port of the receiver, and the control circuit is configured to disable the output of the transmitter for a programmable time period.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- 13. A method of overvoltage protection for a transceiver, the method comprising:
receiving, at a receiver of the transceiver, one or more link pulses and signals; detecting, by the receiver, an overvoltage caused by a link pule; sending, by the receiver, an overvoltage signal to a control circuit; and controlling, by the control circuit, an output of a transmitter of the transceiver in response to the overvoltage signal. wherein; controlling the output of the transmitter comprises disabling the output of the transmitter for a programmable time period, the link pulse is receivable from the transmitter when a link between the transceiver and a far-end transceiver is not active.
- View Dependent Claims (14, 15, 16, 17)
- 18. A wired communication device comprising:
a transmitter configured to transmit signals and link pulses to a far-end device; a receiver including a signal detection circuit configured to detect an overvoltage event and generate an overvoltage signal in response to detection of the overvoltage event; and a control circuit configured to disable an output of the transmitter in response to receiving the overvoltage signal, wherein; the control circuit is configured to disable the output of the transmitter for a programmable time period, and the overvoltage event is caused by a link pulse of the transmitter when a link to the far-end device is not active.
- View Dependent Claims (19, 20)
The present description relates generally to integrated circuits, and more particularly, to fast overvoltage protection circuit with digital control.
New semiconductor integrated circuit (IC) technologies are quite sensitive to overvoltage over active devices. In particular, in new Fin field-effect transistor (FinFET) technologies (e.g., with 16 nm, 10 nm and 7 nm feature sizes) devices are less tolerant to overvoltage events. Therefore, circuits implemented in these technologies need fast overvoltage detection and protection circuits. For example, in wired communication systems, such as Ethernet, handshaking link pulses can, in certain circumstances, cause overvoltage at the transceiver output.
For instance, an Ethernet transmitter (TX) may send signals to a far-end receiver (RX), while at the same time the receiver (RX) may receive signals from the far-end transmitter (TX). In order to build up such a full-duplex link, special high-amplitude link pulses can be sent over a connecting medium (e.g., a cable) such that a far-end receiver can recognize these link pulses and start building the link. At the moment that the link pulses are sent, it is unknown to the transmitting end whether a cable and/or a far-end receiver are present. When no far-end receiver is present, the line impedance is doubled, causing a double-amplitude voltage on the output of the transceiver of the transmitting end, which can possibly damage the internal transistors due to overvoltage.
Certain features of the subject technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the subject technology are set forth in the following figures.
The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced without one or more of the specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the subject technology.
In one or more aspects of the subject technology, systems and configurations are described for providing fast overvoltage protection with digital control. The overvoltage protection of the subject technology enables fast detection of overvoltage situations as well as fast protection against these overvoltage situations. The implementation of the disclosed overvoltage detection and protection technology does not limit analog bandwidth, is digitally programmable, and can be efficiently ported to new technologies.
The apparatus 100 can communicate with the far-end transceiver 180 through a full duplex communication link. For example, the TX 102 can send signals 122 to the far-end transceiver 180, and at the same time, the RX 104 can receive signals 124 from the far-end transceiver 180. In order to establish the full-duplex link, one or more special high-amplitude link pulses are sent onto the cable 126 such that a receiver of the far-end transceiver 180 can recognize the link pulses (e.g., 130) and start building the full duplex link. An example range of values for amplitude of the link pulses 130 is about 1-1.5 V at the transmitter side. In some implementations, at the receiver side, detection levels of about 200-400 mV can be used. At the moment the link pulses are sent, it is unknown whether a cable and/or the far-end transceiver are present (e.g., connected and/or active). When no far-end receiver is present, the line impedance is doubled (e.g., 100Ω), causing a double amplitude pulse 140 on an output port of the TX 102 and/or RX 104, possibly damaging the internal transistors by overvoltage. The receiver 104 can detect the double amplitude pulse 140 that exceed a threshold 160, and upon such a detection, can send an overvoltage pulse 112 to the control circuit 106. An example range of values for an amplitude of the double amplitude pulse 140 is about 2-3 V. This range of values can approximately double when the cable is removed. The control circuit 106, in response, sends a control signal 114 to the TX 102 and cancels transmission of further link pulses 150.
The existing solution analyzes the output of the receiver by a microcontroller running firmware. The microcontroller is responsible for controlling the output amplitude of the transmitter. One shortcoming of the existing solution is that the microcontroller may also be busy performing other tasks, which makes the detection too slow. Further, the amplitude control is too slow for overvoltage mitigation of the transistors in modern integrated circuits (ICs) manufactured using, for example, with Fin field-effect transistor (FinFET) technologies. FinFET devices of at low feature sizes (e.g., 16 nm, 10 nm and 7 nm) are less tolerant to overvoltage events and cannot be protected by the existing slow solution.
In the fast overvoltage protection of the subject technology, the overvoltage is digitally controlled with the control circuit 106, which is a dedicated fast digital control circuit, as described herein, and can reliably protect the less overvoltage tolerant transistors of the modern ICs.
In some implementations, the signal detection circuit 204, can be programmable and be programmed, for example, by programmable threshold level signal 226 provided by a processor. The threshold level signal 226 can control threshold levels 222 and 224 respectively associated with a receive-mode and a link-pulse transmit mode of the signal detection circuit 204. When the signal detection circuit 204 detects a transmitted link-pulse with an amplitude higher than the threshold level 224, the signal detection circuit 204 can provide an overvoltage signal 208. The transmitted link-pulse with the amplitude exceeding the threshold level 224 can be from the TX 102, when the link with far-end transceiver 180 (e.g., through the cable 126 of
The attenuator 310 includes variable resistors RV1 and RV2. The attenuation of the attenuator 310 is controlled by a transmit-mode control signal 304 (e.g., control signal 114 of
As shown in the example implementation 500B, two equally weighted DAC cells 522 and 524 of the unary DAC cells can be combined in pairs to form a DAC 520, which is coupled to a decoder 530. The decoder 530 includes selectors 532 and 534 and inverters 536 and 538. The pairs can be switched by a selection signal 540 between a first mode in which data (D0/D1) is converted and a second mode in which the cells are put in common mode. In the common mode, the differential output (e.g., between Outp and Outn) is zero, but the common mode current stays active such that no common mode transition is observed at the output of the D/A converter.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure.
The predicate words “configured to”, “operable to”, and “programmed to” do not imply any particular tangible or intangible modification of a subject, but, rather, are intended to be used interchangeably. For example, a processor configured to monitor and control an operation or a component may also mean the processor being programmed to monitor and control the operation or the processor being operable to monitor and control the operation. Likewise, a processor configured to execute code can be construed as a processor programmed to execute code or operable to execute code.
A phrase such as an “aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A phrase such as a configuration may refer to one or more configurations and vice versa.
The word “example” is used herein to mean “serving as an example or illustration.” Any aspect or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs.
All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.” Furthermore, to the extent that the term “include,” “have,” or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term “comprise” as “comprise” is interpreted when employed as a transitional word in a claim.