Predistorter for compensating linearity of an amplifier
First Claim
1. A predistorter for compensating linearity of an amplifier, the predistorter comprising:
- a first capacitor having a first end coupled to a first node of the amplifier;
a first bias input circuit configured to receive a first bias;
a second bias input circuit configured to receive a second bias;
a second capacitor; and
an impedance conversion circuit configured to perform an impedance conversion to provide a variable capacitance, the impedance conversion circuit comprising;
a first resistor; and
a field-effect transistor (FET);
wherein a gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, a first end of the second capacitor and a second end of the first resistor, and a second end of the second capacitor is coupled to a second node of the amplifier.
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Abstract
A predistorter has a first capacitor, a first bias input circuit, a second bias input circuit, a second capacitor and an impedance conversion circuit. A first end of the first capacitor is coupled to a first node of the amplifier. The impedance conversion circuit has a first resistor and a field-effect transistor (FET) and is used to perform an impedance conversion to provide a variable capacitance. A gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, and another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, first end of the second capacitor and a second end of the first resistor.
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Citations
10 Claims
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1. A predistorter for compensating linearity of an amplifier, the predistorter comprising:
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a first capacitor having a first end coupled to a first node of the amplifier; a first bias input circuit configured to receive a first bias; a second bias input circuit configured to receive a second bias; a second capacitor; and an impedance conversion circuit configured to perform an impedance conversion to provide a variable capacitance, the impedance conversion circuit comprising; a first resistor; and a field-effect transistor (FET); wherein a gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, a first end of the second capacitor and a second end of the first resistor, and a second end of the second capacitor is coupled to a second node of the amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification