Distributed I/O Interfaces in Modularized Integrated Circuit Devices

• US 20190319627A1
• Filed: 06/28/2019
• Published: 10/17/2019
• Est. Priority Date: 06/28/2019
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chromczak, Jeffrey, Rotker, Paul
• Granted Patent: US 10,879,903 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks

Abstract

An integrated circuit device is disclosed that includes an interposer and a programmable fabric die disposed on the interposer. The programmable fabric die includes multiple sectors that each have multiple rows of logic element blocks. Each row of logic element blocks includes multiple microbumps. Each logic element block has programmable fabric circuitry and an input/output interface electrically coupled to a respective microbump. The integrated circuit device also includes a device disposed on the interposer external to the programmable fabric die and electrically coupled to the microbumps via the interposer.

Claims

1. An integrated circuit device, comprising:

an interposer;

a programmable fabric die disposed on the interposer, wherein the programmable fabric die comprises a plurality of microbumps and a plurality of logic element blocks, wherein the plurality of logic element blocks comprise;

programmable fabric circuitry; and

a plurality of input/output interfaces distributed among the plurality of logic element blocks, wherein the plurality of input/output interfaces is configured to electrically couple to the plurality of microbumps; and

a device disposed on the interposer, wherein the device is external to the programmable fabric die and is configured to electrically couple to the plurality of microbumps via the interposer.

2. The integrated circuit device of claim 1, wherein the device comprises a second programmable fabric die.

3. The integrated circuit device of claim 1, wherein the device comprises an input/output block configured to communicatively couple to an external device, wherein the external device is external to the integrated circuit device.

4. The integrated circuit device of claim 1, wherein a first microbump of the plurality of microbumps is configured to electrically couple to a second microbump of the plurality of microbumps.

5. The integrated circuit device of claim 4, wherein the first microbump is configured to electrically couple to the second microbump via the interposer.

6. The integrated circuit device of claim 4, wherein the first microbump is configured to electrically couple to a first input/output interface of a first logic element block of the plurality of logic element blocks, wherein the second microbump is configured to electrically couple to a second input/output interface of a second logic element block of the plurality of logic element blocks.

7. The integrated circuit device of claim 6, wherein the programmable fabric die comprises a plurality of sectors, wherein a first sector of the plurality of sectors comprises the first logic element block, wherein a second sector of the plurality of sectors comprises the second logic element block.

8. The integrated circuit device of claim 1, wherein the programmable fabric die comprises a plurality of electrostatic discharge diodes, wherein the plurality of microbumps is configured to electrically couple to the plurality of electrostatic discharge diodes.

9. The integrated circuit device of claim 8, wherein the plurality of electrostatic discharge diodes is disposed in one or more columns.

10. A programmable fabric die comprising:

a plurality of microbumps disposed on a bottom surface of the programmable fabric die;

a plurality of logic element blocks; and

a plurality of input/output interfaces distributed among the plurality of logic element blocks, wherein the plurality of input/output interfaces is configured to electrically couple to the plurality of microbumps.

11. The programmable fabric die of claim 10, wherein a first microbump of the plurality of microbumps is configured to electrically couple to a second microbump of the plurality of microbumps.

12. The programmable fabric die of claim 11, wherein the first microbump is configured to electrically couple to the second microbump via one or more wires disposed in an interposer.

13. The programmable fabric die of claim 10, wherein a first microbump of the plurality of microbumps is configured to electrically couple to a second microbump of a second plurality of microbumps of a second programmable fabric die.

14. The programmable fabric die of claim 10, wherein a first microbump of the plurality of microbumps is configured to electrically couple to an input/output block, wherein the input/output block is configured to communicatively couple to an external device.

15. The programmable fabric die of claim 10, comprising a plurality of electrostatic discharge diodes, wherein the plurality of microbumps is electrically coupled to the plurality of electrostatic discharge diodes.

16. The programmable fabric die of claim 15, wherein the plurality of electrostatic discharge diodes is disposed in one or more columns.

17. A programmable fabric die comprising:

a plurality of microbumps; and

a plurality of sectors comprising a plurality of rows of logic element blocks, wherein the plurality of rows of logic element blocks comprises;

programmable fabric circuitry;

a plurality of input/output interfaces distributed among the plurality of rows of logic element blocks, wherein the plurality of input/output interfaces is configured to electrically couple to the plurality of microbumps; and

repair logic configured to reroute an incoming signal from a microbump of the plurality of microbumps to a second row of logic element blocks of the plurality of rows of logic element blocks when a first row of logic element blocks of the plurality of rows of logic element blocks is determined to be faulty.

18. The programmable fabric die of claim 17, wherein the repair logic is configured to reroute the incoming signal by remapping the first row of logic element blocks with the second row of logic element blocks.

19. The programmable fabric die of claim 18, wherein the repair logic comprises one or more fuses that are configured to remap the first row of logic element blocks with the second row by of logic element blocks disconnecting the first row of logic element blocks from the microbump and connecting the second row of logic element blocks to the microbump.

20. The programmable fabric die of claim 17, wherein the repair logic is configured to reroute an outgoing signal from the first row of logic element blocks to a second input/output interface of the plurality of input/output interfaces when a first input/output interface of the plurality of input/output interfaces is determined to be faulty.

21. The programmable fabric die of claim 20, wherein the repair logic is configured to reroute the outgoing signal by remapping the first input/output interface with the second input/output interface.

22. The programmable fabric die of claim 21, wherein the repair logic comprises one or more fuses that are configured to remap the first input/output interface with the second input/output interface by disconnecting the first input/output interface from a row of logic element blocks of the plurality of rows of logic element blocks and connecting the second input/output interface to the row of logic element blocks.