MULTI-MODE CONFIGURABLE TRANSCEIVER WITH LOW VOLTAGE SWITCHES

• US 20190319664A1
• Filed: 05/06/2019
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Shenzhen Goodix Technology Co., Ltd.
• Original Assignee: Shenzhen Goodix Technology Co., Ltd.
• Inventors: Emira, Ahmed, Khatib, Rami, Sivasubramaniam, Janakan, Gagne, Jared
• Granted Patent: US 10,911,091 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/081 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A transceiver includes a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and ground, a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path, and a second transmit path including a high power amplifier and a third switch coupled between the main signal path and ground. The receive path is active when the first, second, and third switches are in an open position, the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

Claims

1. A transceiver comprising:

a receive path including a low noise amplifier and a first switch coupled between the low noise amplifier and a ground potential;

a first transmit path including a low power amplifier and a second switch coupled between the low power amplifier and a main signal path; and

a second transmit path including a high power amplifier and a third switch coupled between the main signal path and the ground potential,

wherein the receive path is active when each of the first switch, the second switch, and the third switch is in an open position,

wherein the first transmit path is active when the first switch is in a closed position, the second switch is in the closed position, and the third switch is in the open position, and

wherein the second transmit path is active when the first switch and the third switch are in the closed position, and the second switch is in the open position.

2. The transceiver of claim 1, further comprising:

a first capacitor coupled between the first switch and the ground potential;

a second capacitor coupled between the main signal path and the low noise amplifier; and

a third capacitor coupled between the second switch and the main signal path.

3. The transceiver of claim 2, further comprising:

a first DC bias circuit coupled to the first capacitor and configured to provide a first DC bias voltage to the low noise amplifier; and

a second DC bias circuit coupled to the second switch and configured to provide a second DC bias voltage to an output of the low power amplifier.

4. The transceiver of claim 1, further comprising:

a logic circuit configured to generate a plurality of control signals for setting the first switch, the second switch, and the third switch between their respective closed position and the open position according to operating modes of the transceiver.

5. The transceiver of claim 4, further comprising:

a first power source voltage coupled to the receive path;

a second power source voltage coupled to the first transmit path;

a third power source voltage coupled to the second transmit path; and

a fourth power source voltage coupled to the logic circuit,

wherein the fourth power source voltage is lower than the first power source voltage, which is lower than the second power source voltage, which is lower than the third power source voltage.

6. The transceiver of claim 5, further comprising:

a first power supply switch configured to provide the first power source voltage to the receive path;

a second power supply switch configured to provide the second power source voltage to the first transmit path; and

a third power supply switch configured to provide the third power source voltage to the second transmit path.

7. The transceiver of claim 1, wherein the second transmit path further comprises:

a balun comprising a primary winding coupled to the high power amplifier and a secondary winding having a first end coupled to the main signal path and a second end coupled to the ground potential through the third switch.

8. The transceiver of claim 7, wherein the primary winding comprises a tap coupled to a power source voltage of the high power amplifier.

9. The transceiver of claim 1, further comprising a matching inductor coupled between the main signal path and the receive path.

10. The transceiver of claim 9, wherein the matching inductor is a part of a balun disposed in the second transmit path.

11. The transceiver of claim 1, wherein the first switch and the third switch each are low voltage n-type field effect transistors, and the second switch is a high voltage n-type field effect transistor.

12. The transceiver of claim 1, wherein each of the first switch and the third switch is a field effect transistor in a core region of the transceiver, and the second switch is a field effect transistor in an input/output region of the transceiver.

13. The transceiver of claim 1, wherein the low noise amplifier, the low power amplifier, the high power amplifier, the first switch, the second switch, and the third switch are integrated in a same integrated circuit.

14. The transceiver of claim 1, wherein the second transmit path further comprises:

a first mixer configured to frequency up-convert a baseband in-phase signal to a radio frequency (RF) in-phase signal;

a second mixer configured to frequency up-convert a baseband quadrature signal to a RF quadrature signal; and

an adder configured to add the RF in-phase signal and the RF quadrature signal to a summed RF signal and provided the summed RF signal to the high power amplifier.

15. The transceiver of claim 14, wherein the summed RF signal is a single-ended signal.

16. The transceiver of claim 14, wherein the summed RF signal is a differential signal.

17. A method of operating a transceiver comprising a receive path having a first switch coupled between a low noise amplifier and a ground potential, a first transmit path having a second switch coupled between a low power amplifier and a main signal path, and a second transmit path having a third switch coupled between a secondary winding of a balun and the ground potential, the method comprising:

selecting the receive path by setting the first switch in an open position, the second switch in the open position, and the third switch in the open position;

selecting the first transmit path by setting the first switch in a closed position, the second switch in the closed position, and the third switch in the open position; and

selecting the second transmit path by setting the first switch in the closed position, the second switch in the open position, and the third switch in the closed position, wherein

the first switch and the third switch are low voltage transistors in a core region and the second switch is a high voltage transistor in an input/output region of the transceiver.

18. The method of claim 17, wherein operating the transceiver comprises:

providing a first DC bias voltage to the receive path, the first DC bias voltage being coupled to the main signal path through an impedance matching inductor; and

providing a second DC bias voltage to the first transmit path, the second DC bias voltage being coupled to the main signal path through a capacitor.

19. The method of claim 17, wherein operating the transceiver comprises:

generating a plurality of control signals, by a logic circuit, for setting the first switch, the second switch, and the third switch between the closed position and the open position.

20. The method of claim 17, wherein:

selecting the receive path comprises providing a first power source voltage to the receive path, disconnecting a second power source voltage to the first transmit path, and disconnecting a third power source voltage to the second transmit path;

selecting the first transmit path comprises providing the second power source voltage to the first transmit path, disconnecting the first power source voltage to the receive path, and disconnecting the third power source voltage the second transmit path; and

selecting the second transmit path comprises providing the third power source voltage to the second transmit path, disconnecting the first power source voltage to the receive path, and disconnecting the second power source voltage to the first transmit path.