×

Techniques For Determining Timestamp Inaccuracies In A Transceiver

  • US 20190319729A1
  • Filed: 06/21/2019
  • Published: 10/17/2019
  • Est. Priority Date: 06/21/2019
  • Status: Active Grant
First Claim
Patent Images

1. An integrated circuit comprising:

  • a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function specified by a data transmission protocol, wherein the transceiver circuit is coupled to receive packets of timing test patterns, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns, and wherein each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns; and

    a memory circuit that stores each of the timestamps generated by the stage circuits in response to the trigger generated by a respective one of the stage circuits, wherein the memory circuit outputs the timestamps.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×