Techniques For Determining Timestamp Inaccuracies In A Transceiver
First Claim
1. An integrated circuit comprising:
- a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function specified by a data transmission protocol, wherein the transceiver circuit is coupled to receive packets of timing test patterns, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns, and wherein each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns; and
a memory circuit that stores each of the timestamps generated by the stage circuits in response to the trigger generated by a respective one of the stage circuits, wherein the memory circuit outputs the timestamps.
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Abstract
An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.
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Citations
20 Claims
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1. An integrated circuit comprising:
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a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function specified by a data transmission protocol, wherein the transceiver circuit is coupled to receive packets of timing test patterns, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns, and wherein each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns; and a memory circuit that stores each of the timestamps generated by the stage circuits in response to the trigger generated by a respective one of the stage circuits, wherein the memory circuit outputs the timestamps. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A data transmission system comprising:
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a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function according to a data transmission protocol, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving a packet comprising a test pattern; a memory circuit that stores the timestamps generated by the stage circuits; and a post processor circuit that receives the timestamps from the memory circuit, wherein the post processor circuit analyzes the timestamps to determine which of the stage circuit are generating inaccuracies in the timestamps, and wherein the post processor circuit calculates values for the inaccuracies identified in the timestamps. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for determining inaccuracies in timestamps generated according to a data transmission protocol, the method comprising:
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receiving packets comprising test patterns at a transceiver circuit, wherein the transceiver circuit comprises stage circuits, and wherein each of the stage circuits in the transceiver circuit performs at least one function according to the data transmission protocol; generating a timestamp at each of the stage circuits in the transceiver circuit upon receipt of each of the packets; generating a trigger at each of the stage circuits in the transceiver circuit that indicates when each of the packets is received at a respective one of the stage circuits; and storing each of the timestamps generated by the stage circuits in a memory circuit in response to the trigger generated by the respective one of the stage circuits. - View Dependent Claims (17, 18, 19, 20)
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Specification