Techniques For Determining Timestamp Inaccuracies In A Transceiver

• US 20190319729A1
• Filed: 06/21/2019
• Published: 10/17/2019
• Est. Priority Date: 06/21/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Leong, Han Hua, Mallela, Sita Rama Chandrasekhar, Hafeez, Muhammad Kazim, Chen, Ming-Shiung, Agrawal, Anuj
• Granted Patent: US 11,652,561 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Claims

1. An integrated circuit comprising:

a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function specified by a data transmission protocol, wherein the transceiver circuit is coupled to receive packets of timing test patterns, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns, and wherein each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns; and

a memory circuit that stores each of the timestamps generated by the stage circuits in response to the trigger generated by a respective one of the stage circuits, wherein the memory circuit outputs the timestamps.

2. The integrated circuit of claim 1 further comprising:

a multiplexer circuit that provides each of the timestamps and each of the triggers from the transceiver circuit to the memory circuit.

3. The integrated circuit of claim 1, wherein the memory circuit comprises a functional packet generator that generates the packets of timing test patterns using a vector of random access memory programmed as a protocol-specific functional generator of the packets of timing test patterns.

4. The integrated circuit of claim 3 further comprising:

a multiplexer circuit configurable to provide the packets of timing test patterns from either the memory circuit or from a source external to the transceiver circuit.

5. The integrated circuit of claim 1 further comprising:

a calculation circuit that calculates a frequency offset for a clock signal based on the timestamps generated by the stage circuits or based on a timestamp difference indicated by the triggers.

6. The integrated circuit of claim 5 further comprising:

a timestamp computation circuit that adjusts a frequency of the clock signal based on the frequency offset, wherein the timestamp computation circuit uses the clock signal to generate a time of day value.

7. The integrated circuit of claim 1 further comprising:

a time of day circuit that calculates an offset to a time of day value based on the timestamps generated by the stage circuits or a timestamp difference indicated by the triggers; and

a timestamp computation circuit that synchronizes the time of day value with an additional time of day value generated by a master device using the offset to the time of day value.

8. The integrated circuit of claim 1 further comprising:

a timestamp computation circuit that outputs timestamps for messages exchanged with a master device; and

an accuracy binning module that segregates the timestamps generated by the stage circuits in bins based on a measured accuracy range of the timestamps generated by the stage circuits compared to the timestamps output by the timestamp computation circuit.

9. A data transmission system comprising:

a transceiver circuit that comprises stage circuits, wherein each of the stage circuits in the transceiver circuit performs at least one function according to a data transmission protocol, wherein each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving a packet comprising a test pattern;

a memory circuit that stores the timestamps generated by the stage circuits; and

a post processor circuit that receives the timestamps from the memory circuit, wherein the post processor circuit analyzes the timestamps to determine which of the stage circuit are generating inaccuracies in the timestamps, and wherein the post processor circuit calculates values for the inaccuracies identified in the timestamps.

10. The data transmission system of claim 9, wherein the post processor circuit determines a difference between a delay indicated by a first subset of the timestamps generated by a transmitter circuit and a delay indicated by a second subset of the timestamps generated by a receiver circuit to identify an inaccuracy in the timestamps.

11. The data transmission system of claim 9, wherein each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in the packet, and wherein the memory circuit stores each of the timestamps generated by the stage circuits in response to the trigger generated by a respective one of the stage circuits.

12. The data transmission system of claim 11 further comprising:

a time of day circuit that calculates an offset to a time of day value based on the timestamps generated by the stage circuits or based on a timestamp difference indicated by the triggers.

13. The data transmission system of claim 12 further comprising:

a timestamp computation circuit that synchronizes the time of day value with an additional time of day value generated by a master device using the offset to the time of day value.

14. The data transmission system of claim 11 further comprising:

a calculation circuit that calculates a frequency offset for a clock signal based on the timestamps generated by the stage circuits or based on a timestamp difference indicated by the triggers.

15. The data transmission system of claim 14 further comprising:

a timestamp computation circuit that adjusts a frequency of the clock signal based on the frequency offset, wherein the timestamp computation circuit uses the clock signal to generate a time of day value.

16. A method for determining inaccuracies in timestamps generated according to a data transmission protocol, the method comprising:

receiving packets comprising test patterns at a transceiver circuit, wherein the transceiver circuit comprises stage circuits, and wherein each of the stage circuits in the transceiver circuit performs at least one function according to the data transmission protocol;

generating a timestamp at each of the stage circuits in the transceiver circuit upon receipt of each of the packets;

generating a trigger at each of the stage circuits in the transceiver circuit that indicates when each of the packets is received at a respective one of the stage circuits; and

storing each of the timestamps generated by the stage circuits in a memory circuit in response to the trigger generated by the respective one of the stage circuits.

17. The method of claim 16 further comprising:

determining inaccuracies in the timestamps generated by the stage circuits in the transceiver circuit using a post processor circuit by analyzing the timestamps to determine which of the stage circuits are generating the inaccuracies in the timestamps and calculating values for the inaccuracies identified in the timestamps.

18. The method of claim 16 further comprising:

calculating an offset to a time of day value with a time of day circuit based on the timestamps generated by the stage circuits or based on a timestamp difference indicated by the triggers; and

using the offset to the time of day value to synchronize the time of day value with a master time of day value using a timestamp computation circuit.

19. The method of claim 16 further comprising:

calculating a frequency offset for a clock signal based on the timestamps generated by the stage circuits or a timestamp difference indicated by the triggers;

adjusting a frequency of the clock signal using the frequency offset; and

generating a time of day value in response to the clock signal using a timestamp computation circuit.

20. The method of claim 16 further comprising:

outputting timestamps for messages exchanged with a master device from a timestamp computation circuit; and

segregating the timestamps generated by the stage circuits in bins based on a measured accuracy range of the timestamps generated by the stage circuits compared to the timestamps output by the timestamp computation circuit.