LOW LATENCY POST-QUANTUM SIGNATURE VERIFICATION FOR FAST SECURE-BOOT
First Claim
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1. An apparatus, comprising:
- a computer readable memory;
an XMSS verification manager logic to manage XMSS verification functions;
a one-time signature and public key generator logic;
a chain function logic to implement chain function algorithms;
a low latency SHA3 hardware engine; and
a register bank communicatively coupled to the XMSS verification manager logic.
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Abstract
In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
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Citations
20 Claims
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1. An apparatus, comprising:
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a computer readable memory; an XMSS verification manager logic to manage XMSS verification functions; a one-time signature and public key generator logic; a chain function logic to implement chain function algorithms; a low latency SHA3 hardware engine; and a register bank communicatively coupled to the XMSS verification manager logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An electronic device, comprising:
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a processor; and a hardware accelerator for an authentication logic, the hardware accelerator comprising; a computer readable memory; an XMSS verification manager logic to manage XMSS verification functions; a one-time signature and public key generator logic; a chain function logic to implement chain function algorithms; a low latency SHA3 hardware engine; and a register bank communicatively coupled to the XMSS verification manager logic. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification