LOW LATENCY POST-QUANTUM SIGNATURE VERIFICATION FOR FAST SECURE-BOOT

• US 20190319796A1
• Filed: 06/28/2019
• Published: 10/17/2019
• Est. Priority Date: 06/28/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: GHOSH, SANTOSH, Suresh, Vikram, Mathew, Sanu, Sastry, Manoj, Reinders, Andrew H., Kumar, Raghavan, Misoczki, Rafael
• Granted Patent: US 11,405,213 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/0852 Quantum cryptography transmission systems employing electromagnetic waves other than radio waves, e.g. light, infrared H04B10/00; wavelength-division multiplex systems H04J14/02; WDM arrangements H04J14/03
• CPC Class Codes: H04L 9/0877 using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM]
• CPC Class Codes: H04L 9/30 Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
• CPC Class Codes: H04L 9/3236 using cryptographic hash functions
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees

Abstract

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

Claims

1. An apparatus, comprising:

a computer readable memory;

an XMSS verification manager logic to manage XMSS verification functions;

a one-time signature and public key generator logic;

a chain function logic to implement chain function algorithms;

a low latency SHA3 hardware engine; and

a register bank communicatively coupled to the XMSS verification manager logic.

2. The apparatus of claim 1, further comprising logic to:

receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and

apply the set of XMSS inputs to an XMSS verification manager logic.

3. The apparatus of claim 2, further comprising logic to:

assert a busy signal on a communication bus; and

switch to a protected mode in which external read/write operations are disregarded.

4. The apparatus of claim 3, further comprising logic to:

apply a one-time signature function process to the set of XMSS inputs; and

invoke the chain function logic to apply a chain function to facilitate the one-time signature function.

5. The apparatus of claim 1, wherein the SHA3 hardware engine is capable to perform a SHAKE-128 function or to perform a SHAKE-256 operation.

6. The apparatus of claim 5, wherein the SHA3 hardware engine comprises a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a 256 bit message input.

7. The apparatus of claim 6, wherein the SHA3 hardware engine comprises logic to:

perform a first set of 24 SHA3 rounds using the first set of inputs; and

generate a first 128 bit output.

8. The apparatus of claim 7, wherein the SHA3 hardware engine comprises logic to:

perform a second set of 24 SHA3 rounds using no inputs; and

generate a second 128 bit output.

9. The apparatus of claim 6, wherein the SHA3 hardware engine comprises logic to:

perform a first set of 24 SHA3 rounds using the first set of inputs; and

generate a first 256 bit output.

10. The apparatus of claim 9, wherein the SHA3 hardware engine comprises logic to:

perform a second set of 24 SHA3 rounds using no inputs; and

generate a second 256 bit output.

11. An electronic device, comprising:

a processor; and

a hardware accelerator for an authentication logic, the hardware accelerator comprising;

a computer readable memory;

an XMSS verification manager logic to manage XMSS verification functions;

a one-time signature and public key generator logic;

a chain function logic to implement chain function algorithms;

a low latency SHA3 hardware engine; and

a register bank communicatively coupled to the XMSS verification manager logic.

12. The electronic device of claim 11, the hardware accelerator further comprising logic to:

receive, in the computer readable memory, a set of XMSS inputs for an XMSS operation; and

apply the set of XMSS inputs to an XMSS verification manager logic.

13. The electronic device of claim 12, the hardware accelerator further comprising logic to:

assert a busy signal on a communication bus; and

switch to a protected mode in which external read/write operations are disregarded.

14. The electronic device of claim 13, the hardware accelerator further comprising logic to:

apply a one-time signature function process to the set of XMSS inputs; and

invoke the chain function logic to apply a chain function to facilitate the one-time signature function.

15. The electronic device of claim 11, wherein the SHA3 hardware engine is capable to perform a SHAKE-128 function or to perform a SHAKE-256 operation.

16. The electronic device of claim 15, wherein the SHA3 hardware engine comprises a 1600 bit state register to receive a first set of inputs for each WOTS chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, and a 256 bit message input.

17. The electronic device of claim 16, wherein the SHA3 hardware engine comprises logic to:

perform a first set of 24 SHA3 rounds using the first set of inputs; and

generate a first 128 bit output.

18. The electronic device of claim 17, wherein the SHA3 hardware engine comprises logic to:

perform a second set of 24 SHA3 rounds using no inputs; and

generate a second 128 bit output.

19. The electronic device of claim 16, wherein the SHA3 hardware engine comprises logic to:

perform a first set of 24 SHA3 rounds using the first set of inputs; and

generate a first 256 bit output.

20. The electronic device of claim 19, wherein the SHA3 hardware engine comprises logic to:

perform a second set of 24 SHA3 rounds using no inputs; and

generate a second 256 bit output.