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LOW LATENCY POST-QUANTUM SIGNATURE VERIFICATION FOR FAST SECURE-BOOT

  • US 20190319796A1
  • Filed: 06/28/2019
  • Published: 10/17/2019
  • Est. Priority Date: 06/28/2019
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a computer readable memory;

    an XMSS verification manager logic to manage XMSS verification functions;

    a one-time signature and public key generator logic;

    a chain function logic to implement chain function algorithms;

    a low latency SHA3 hardware engine; and

    a register bank communicatively coupled to the XMSS verification manager logic.

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