Low Cost Design For Test Architecture

• US 20190324083A1
• Filed: 05/05/2019
• Published: 10/24/2019
• Est. Priority Date: 12/31/2015
• Status: Active Grant

• Current Assignee: Chinsong Sul
• Original Assignee: Chinsong Sul
• Inventors: Sul, Chinsong
• Granted Patent: US 10,712,388 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.

Claims

1. A modular test method for composition of test patterns for integrated circuits comprising:

the integrated circuit being a target system that has subsystems;

disabling an environment constraint test instrument (ECTI);

generating disabled zero-biased test patterns according to a test protocol;

generating a environment constraint environment (ECE) test using the ECTI and an output encoding function such that

for a first condition, when an environment constraint test enable signal can be set to logic value 1 by replacing values of inputs specified in the zero-biased test patterns, generating an info file for (test pattern) input value replacement, and

for a second condition, when the environment constraint test enable signal cannot be set to logic value 1 by replacing values in the zero-biased test patterns,

enabling the ECTI, and

generating enabled zero-biased test patterns according to the test protocol;

forming target test patterns using the zero-biased test patterns and the ECE test; and

generating an interconnection scheme according to an output translation layer.

2. A modular test method, as in claim 1, wherein generating disabled zero-biased test patterns is a predetermined pattern.

3. A modular test method, as in claim 1, when the first condition is met, the test protocol comprising:

initializing the ECE test by providing an input vector v′

according to a given test specification of the circuit under test;

delivering test data to scan-able flip-flops, wherein the scan-able flip-flops include primary inputs, primary outputs and a translation vector register;

updating the translation vector register to recover a translation vector of arbitrary input g(x);

executing the test;

updating to recover the input to the translation vector register; and

repeating the steps of delivering, uploading, and executing until all test patterns are generated.

4. A modular test method, as in claim 3, delivering test data comprising:

loading test input to the scan-able flip-flops including translation vector registers that correspond to the circuit under test; and

measuring test output of the scan-able flip-flops including translation vector registers.

5. A modular test method, as in claim 3, executing the test comprising:

forcing a functional primary input to be zero;

measuring the corresponding functional output;

launching the delivered test stimulus; and

capturing the test response into scan-able flip flops.

6. A modular test method as in claim 3, the test output encoding further including testing of environment constraints and interconnections.

7. A modular test method, as in claim 1, wherein composition of a given set of zero-biased test patterns with respect to a corresponding IO connectivity of subsystems, calculating a test sequence based on the connectivity of subsystems to attain environment-independent test patterns of the target system.

8. A modular test method, as in claim 7, further comprising replacing functional inputs values in test patterns of each subsystem with its environment constraints to attain environment-incorporated test patterns of the target system.