PHOTONIC ENGINE PLATFORM UTILIZING EMBEDDED WAFER LEVEL PACKAGING INTEGRATION

• US 20190324223A1
• Filed: 12/29/2016
• Published: 10/24/2019
• Est. Priority Date: 12/29/2016
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yim, Myung Jin, Kim, Sang Yup
• Application Number:
  US16/465,003
• Publication Number:
  US 20190324223A1
• Time in Patent Office: Days
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/4232 using the surface tension of fluid solder to align the elements, e.g. solder bump techniques flip-chip mounting techniques in assembly of semiconductor devices H01L24/81
• CPC Class Codes: G02B 6/4239 Adhesive bonding; Encapsulation with polymer material
• CPC Class Codes: G02B 6/4246 Bidirectionally operating package structures
• CPC Class Codes: G02B 6/43 Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92224 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/00 : Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/04 : Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H04B 10/50 : Transmitters
• CPC Class Codes: H04B 10/60 : Receivers

Abstract

Methods/structures of forming package structures are described. Those methods/structures may include a mold material, wherein a plurality of die are embedded in the mold material, a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate, at least one optical die disposed on the package substrate, and a thermal solution disposed on a top surface of the optical die.

Claims

1-25. -25. (canceled)

26. A microelectronic package structure comprising:

a device structure comprising at least one die at least partially embedded in a mold material;

a package substrate, wherein the device structure is at least partially embedded in the package substrate; and

at least one optical die disposed on the package substrate, wherein the at least one optical die is electrically coupled to the at least one die disposed in the molding compound.

27. The microelectronic package structure of claim 26, wherein the at least one optical die comprises a die selected from the group consisting of a transmission die, a receiver die, and a clock and data recovery die.

28. The microelectronic package structure of claim 26, wherein the device structure comprises a system on a chip.

29. The microelectronic package structure of claim 26, wherein the package structure comprises a portion of a photonic engine block.

30. The microelectronic package structure of claim 26, wherein the at least one optical die comprises at least one of an optical transmission die or an optical receiver die.

31. The microelectronic package structure of claim 26, wherein the device structure comprises redistribution layer structures coupling the at least one die.

32. The microelectronic package structure of claim 26, wherein the device structure is embedded in the package substrate.

33. The microelectronic package structure of claim 26, wherein the optical die are electrically coupled to an optical alignment assembly.

34. A microelectronic package structure comprising:

a mold material, wherein a plurality of die are embedded in the mold material;

a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate;

at least one optical die disposed on the package substrate; and

a thermal solution disposed on a top surface of the optical die.

35. The microelectronic package structure of claim 34, wherein the thermal solution comprises a heat sink.

36. The microelectronic package structure of claim 34, wherein the package structure comprises a thermal slug on a bottom surface of the package substrate.

37. The microelectronic package structure of claim 36, wherein a thermal interface material is disposed between a bottom surface of the substrate and the thermal slug.

38. The microelectronic package structure of claim 34, wherein an optical alignment assembly is coupled with the at least one optical die.

39. The microelectronic package structure of claim 34, wherein the plurality of die disposed in the mold material comprise an embedded wafer level ball grid array structure.

40. The microelectronic package structure of claim 39, wherein the embedded wafer level ball grid array structure comprises a redistribution layer disposed between the at least one die.

41. The microelectronic package structure of claim 40, wherein the optical die is electrically and physically coupled to a driver die.

42. A method of forming a microelectronic package structure, comprising:

placing at least one repopulated die on a wafer, wherein the at least one repopulated die comprises at least one each of a driver die, a clock and data recovery die, and a microprocessor die, and wherein the at least one repopulated die are adjacent each other and embedded in a mold material;

forming redistribution conductive structures to electrically couple the repopulated die to each other on the wafer;

singulating the wafer, wherein a singulated die comprises the driver die, the CDR die, and the microprocessor die, and attaching the singulated die to a package substrate; and

attaching at least one optical die on a top surface of the package substrate.

43. The method of claim 42 further comprising wherein the at least one optical die comprise at least one optical transmission die and optical receiver die.

44. The method of claim 43, wherein the at least one optical transmission die is disposed on the driver die, and the at least one receiver die is disposed on a trans impedance amplification die that is disposed within the mold compound and adjacent a receiver clock and data recovery die.

45. The method of claim 42 further comprising wherein the clock and data recovery CDR comprises one of a transmission clock and data recovery or a receiver clock and data recovery die.

46. The method of claim 42 further comprising attaching a heat spreader on the optical die.

47. The method of claim 42 further comprising attaching a thermal slug onto a bottom portion of the substrate.

48. The method of claim 42 further comprising attaching an optical alignment apparatus to a portion of the optical die.

49. The method of claim 42 further comprising wherein attaching the singulated die to the substrate comprises embedding the singulated die into the package substrate.

50. The method of claim 42 wherein attaching the singulated die to the substrate comprises attaching the singulated substrate to a top surface of the package substrate, and forming through mold vias through the mold material to physically couple the singulated die to the package substrate.