OFFLOAD DEFRAG OPERATION FOR HOST-MANAGED STORAGE

• US 20190324683A1
• Filed: 06/29/2019
• Published: 10/24/2019
• Est. Priority Date: 06/29/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LI, Peng, KHAN, Jawad B., TRIKA, Sanjeev N.
• Granted Patent: US 11,042,323 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host'"'"'s DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

Claims

1. Memory device circuitry, comprising:

a controller to control a non-volatile memory (“

NVM”

); and

a memory to store a mapping of a physical address of a contiguous block of memory within a source band of the NVM to a status of data contained in the contiguous block of memory, the status one of a valid status and an invalid status; and

the controller to defragment the source band to a target band separate from the source band based on the mapping, including to relocate data having the valid status from the contiguous block of memory within the source band to another contiguous block of memory within the target band.

2. The memory device circuitry of claim 1, wherein:

the contiguous block of memory is one of a plurality of units of contiguous logical block addresses (LBAs) within the source band; and

the mapping is a bitmap stored in a region of the memory protected from a power-loss-interrupt (PLI), an entry of the bitmap corresponding to one of the plurality of units of contiguous LBAs within the source band.

3. The memory device circuitry of claim 2, wherein:

the source band and target band each comprise a band of physical pages in the NVM

each unit of the plurality of units of contiguous LBAs is an indirection unit (IU) aligned at a physical address of a physical page in the band of physical pages in the NVM; and

each entry of the bitmap corresponds to the physical address at which an IU is aligned, an entry to indicate a status of the data contained in the IU, the status any one of the valid status and the invalid status.

4. The memory device circuitry of claim 3, wherein to defragment the source band to the target band based on the mapping, the controller is to:

determine the status of data contained in an IU aligned at a source physical address based on the entry of the bitmap corresponding to the source physical address;

relocate the data determined to have the valid status to an IU aligned to a target physical address; and

update the entry of the bitmap corresponding to the source physical address to an invalid status.

5. The memory device circuitry of claim 4, wherein the controller to defragment the source band responsive to a command received from the host to defragment the source band, the command to specify the source band and any one or more of an available target band and the bitmap, including the bitmap stored in a context safe region of memory in the host.

6. The memory device circuitry of claim 5, wherein the controller is further to:

notify the host that the command to defragment the source band is complete;

generate a list mapping a logical address index of the plurality of units of contiguous LBAs in the IU with the target physical address to which the data in the IU was relocated; and

provide the list to the host.

7. The memory device circuitry of claim 6, wherein the source band specified in the command received from the host is based on:

an indirection table to map the logical address index of an LBA to the physical address at which the IU containing the LBA is aligned, the logical address index representing a logical block address in the NVM,

an invalidity table to track a level of invalidity of the source band, the level of invalidity based on how many IUs are aligned with source physical addresses mapped to the invalid status as compared to the valid status, and

the host having determined that the level of invalidity of the source band triggered the request to defragment the source band; and

further wherein the list enables the host to update the indirection table with the target physical address to which the data in the IU was relocated.

8. The memory device circuitry of claim 4, wherein the command received from the host is a command descriptor to include any of:

an offset to a region of memory accessible to both the controller and the host,

a size of the command,

an index of the source band to be defragmented,

an index of the target band where the data is to be relocated, and

an offset to the index of the target band.

9. The memory device circuitry of claim 8, wherein the command descriptor received from the host is stored in the region of memory accessible to both the controller and the host via direct memory access (DMA).

10. The memory device circuitry of claim 8, wherein the NVM is arranged in any of a solid-state storage device (SSD) and a hybrid SSD.

11. The memory device circuitry of claim 1, the controller further to:

store an index to the target band in a power-loss-interrupt (PLI) safe region of the NVM;

erase any data relocated to the target band upon detecting a PLI; and

notify the host that the command to defragment the source band is not complete.

12. The memory device circuitry of claim 11, wherein the PLI safe region of the NVM includes any of a DRAM region, an SRAM region and a three-dimensional cross-point media, the controller further to store the mapping in the PLI safe region of the memory.

13. A storage system, comprising

non-volatile media;

and

logic coupled to the non-volatile media to;

receive a request from a host managing the non-volatile media to defragment a band of contiguous data in the non-volatile media from a source band to a target band separate from the source band, and

defragment the source band to the target band based on a status of data within the source band, the status one of a valid status and an invalid status tracked for data located at physical addresses within the band of contiguous data.

14. The storage system of claim 13, wherein the logic coupled to the non-volatile media further to:

notify the host that the request to defragment the source band is complete;

generate a list mapping logical address indices of contiguous logical block addresses of the band of contiguous data with physical addresses in the target band to which the source band was defragmented; and

provide the list to the host.

15. The storage system of claim 13, further comprising:

a map to track the status of data located at the physical addresses within the band of contiguous data, wherein the map is;

maintained in any of;

a protected region of memory coupled to the host managing the non-volatile media,

a region of a memory coupled to the non-volatile media; and

specified in the request; and

updated to invalidate the status of data relocated from the physical addresses within the band of contiguous data responsive to the request.

16. The storage system of claim 15, wherein the region of memory coupled to the non-volatile media is protected from a power-loss-interrupt (PLI).

17. The storage system of claim 15, wherein the map to track the status of data located at physical addresses within the band is a bitmap, each entry of the bitmap to:

correspond to a unit of contiguous logical block addresses aligned at one of the physical addresses within the band; and

store any one of a true value for the valid status and a false value for the invalid status.

18. The storage system of claim 17, wherein the unit of contiguous logical block addresses aligned at one of the physical addresses within the band is an indirection unit (IU).

19. The storage system of claim 13, wherein the request from the host to specify the source band to be defragmented and one or more target bands into which the source band is to be defragmented.

20. At least one machine-readable medium comprising a plurality of instructions executable by a system to cause the system to:

defragment a band of contiguous data in a non-volatile media from a source band to a target band separate from the source band responsive to a request from a host managing the non-volatile media;

wherein the source band is defragmented to the target band based on a status of data within the source band, the status one of a valid status and an invalid status tracked for data located at physical addresses within the band of contiguous data.

21. The at least one machine-readable medium of claim 20, wherein the plurality of instructions further cause the system to:

notify the host that the request to defragment the source band is complete;

generate a list mapping logical address indices of contiguous logical block addresses of the band of contiguous data with physical addresses in the target band to which the source band was defragmented; and

provide the list to the host.

22. The at least one machine-readable medium of claim 20, wherein the plurality of instructions further cause the system to:

track the status of data located at the physical addresses within the band of contiguous data in a map, the map specified in the request;

maintain the map in any of;

a protected region of memory coupled to the host managing the non-volatile media,

a region of a memory coupled to the non-volatile media; and

update the map to invalidate the status of data relocated from the physical addresses within the band of contiguous data responsive to the request.

23. The at least one machine-readable medium of claim 22, wherein the region of memory coupled to the non-volatile media is protected from a power-loss-interrupt (PLI).

24. The at least one machine-readable medium of claim 22, wherein the map to track the status of data located at physical addresses within the band is a bitmap, each entry of the bitmap to:

correspond to a unit of contiguous logical block addresses aligned at one of the physical addresses within the band; and

store any one of a true value for the valid status and a false value for the invalid status.

25. The at least one machine-readable medium of claim 24, wherein the unit of contiguous logical block addresses aligned at one of the physical addresses within the band is an indirection unit (IU) comprising a plurality of logical block addresses maintained in the host in a logical to physical indirection table.