STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR STORING PROGRAM

• US 20190324692A1
• Filed: 03/29/2019
• Published: 10/24/2019
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: KUWAMURA, Shinya
• Granted Patent: US 11,074,012 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A storage device includes: a semiconductor memory; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory, wherein the memory controller is configured to store information for translating a logical address into a physical address, and execute a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.

Claims

1. A storage device comprising:

a semiconductor memory; and

a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory,

wherein the memory controller is configured to

store information for translating a logical address into a physical address, and

execute a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.

2. The storage device according to claim 1,

wherein the memory controller is configured to create a plurality of second computational commands based on a single first computational command that specifies an address destination in the semiconductor memory by using a logical address, each of the plurality of second computational commands being configured to specify access destinations in the semiconductor memory on a per-data access size basis, and

in accordance with the second computational command, process data stored in the semiconductor memory on the per-data access size basis.

3. The storage device according to claim 1,

wherein the memory controller is configured to receive the information from a transmission source device of the computational command.

4. The storage device according to claim 3,

wherein the memory controller is configured to receive, prior to executing the computational command, a part of the information to be used for processing of the computational command, from the transmission source device of the computational command.

5. A system comprising:

an information processing device; and

a storage device coupled to the information processing device, the storage device including a semiconductor memory and a memory controller, the memory controller being configured to control the semiconductor memory,

wherein the information processing device is configured to issue a computational command to the storage device, and

wherein the memory controller of the storage device is configured to

store information for translating a logical address into a plurality of physical addresses, and

execute a dividing process that includes dividing, upon receiving the computational command from the information processing device, the computational command into a plurality of commands based on the information.

6. A non-transitory computer-readable storage medium for storing a program which causes a processor to perform processing for controlling a semiconductor memory, the processing comprising:

storing information for translating a logical address into a physical address, and

executing a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.