TECHNOLOGIES FOR ENSURING FUNCTIONAL SAFETY OF AN ELECTRONIC DEVICE

• US 20190324751A1
• Filed: 06/29/2019
• Published: 10/24/2019
• Est. Priority Date: 06/29/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Boschi, Gabriele, Campinoti, Alessandro
• Granted Patent: US 10,949,203 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1637 using additional compare functionality in one or some but not all of the redundant processing components
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1675 Temporal synchronisation or re-synchronisation of redundant processing components
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

Technologies for ensuring functional safety of an electronic device include receiving data by a primary and secondary hardware unit and performing a function on the data. Each of the primary and secondary hardware unit perform the same function on their respective set of data to generate corresponding results. A determination is made whether the hardware units are synchronized and the results can be compared. If so, the results are compared and an alert is generated if the results do not match.

Claims

1. An electronic system for ensuring functional safety of an electronic device, the electronic system comprising:

a primary hardware unit having a set of first data registers and a first function logic to perform a function using data stored in the set of first data registers to generate a first result; and

a secondary hardware unit having a set of second data registers, a second function logic to perform the function using data stored in the set of second data registers to generate a second result, and a comparator to compare the first result and the second result,

wherein the comparator is controllable to perform the comparison between the first result and the second result based on a determination to perform the comparison.

2. The electronic system of claim 1, further comprising controller logic to determine whether to perform the comparison between the first result and the second result based on a criteria, the controller logic having an output connected to the comparator to provide an enable signal to an enable input of the comparator to cause the comparator to perform the comparison.

3. The electronic system of claim 2, wherein the controller logic is to determine whether to perform the comparison between the first result and the second result based on an elapsed time since the last reset of the secondary hardware unit.

4. The electronic system of claim 2, wherein the controller logic is to determine whether to perform the comparison between the first result and the second result based on an analysis of data stored in the set of second data registers.

5. The electronic system of claim 4, wherein the controller logic is to determine whether to perform the comparison between the first result and the second result based on an elapsed time since data was written to the second set of data registers.

6. The electronic system of claim 1, further comprising a timeout manager to generate an alert in response to a determination that the comparator has not been enabled to perform the comparison within a reference time period since a reference point in time.

7. The electronic system of claim 6, wherein the timeout manager is to compare a timer to the reference time period to determine whether the comparator has been enabled within the reference time period and wherein the timer is reset in response to a reset of the secondary hardware unit.

8. The electronic system of claim 1, further comprising data process logic to process the first result received from the primary hardware unit prior to comparison of the first result to the second result by the comparator.

9. The electronic system of claim 1, wherein the primary hardware unit is a first processor core of a processor and the secondary hardware unit is a second processor core of the processor.

10. A method for ensuring functional safety of an electronic device, the method comprising:

receiving data by a primary hardware unit of an electrical system of the electronic device;

storing, by the primary hardware unit, the data in a set of first data registers of the primary hardware unit;

receiving the data by a secondary hardware unit of the electrical system;

storing, by the secondary hardware unit, the data in a set of second data registers of the secondary hardware unit;

performing, by the primary hardware unit, a function using the data stored in the set of first data registers to generate a first result;

performing, by the secondary hardware unit, the function using the data stored in the set of second data registers to generate a second result;

determining whether to perform a comparison of the first result and the second result; and

controlling, in response to a determination to perform the comparison, a comparator of the secondary hardware unit to perform the comparison of the first result and the second result.

11. The method of claim 10, wherein determining whether to perform the comparison comprises determining, by controller logic, whether to perform the comparison based on a criteria and providing an enable signal to the comparator to cause the comparator to perform the comparison in response to a determination that the perform the comparison.

12. The method of claim 11, wherein determining whether to perform the comparison comprises determining whether to perform the comparison based on an elapsed time since a reference point in time.

13. The method of claim 11, wherein determining whether to perform the comparison comprises determining whether to perform the comparison based on an analysis of data stored in the set of second data registers.

14. The method of claim 13, wherein determining whether to perform the comparison comprises determining whether to perform the comparison based on an elapsed time since data was written to the second set of data registers.

15. The method of claim 10, further comprising generating, by the secondary hardware unit, an alert in response to a determination that the comparator has not been enabled to perform the comparison within a reference time period since a last reset of the secondary hardware unit.

16. The method of claim 15, wherein generating the alert comprises comparing a timer to the reference time period to determine whether the comparator has been enabled within the reference time period,

and further comprising resetting the timer in response to a reset of the secondary hardware unit.

17. The method of claim 10, further comprising processing, by the secondary hardware unit, the first result received from the primary hardware unit prior to comparison of the first result to the second result by the comparator.

23. The one or more machine-readable storage media of claim 10, wherein the plurality of instructions, when executed, further cause the secondary hardware unit to generate an alert in response to a determination that the comparator has not been enabled to perform the comparison within a reference time period since a last reset of the secondary hardware unit.

24. The one or more machine-readable storage media of claim 23, wherein to generate the alert comprises to compare a timer to the reference time period to determine whether the comparator has been enabled within the reference time period,

wherein the plurality of instructions, when executed, further cause the secondary hardware unit to reset the timer in response to a reset of the secondary hardware unit.

25. The one or more machine-readable storage media of claim 10, wherein the plurality of instructions, when executed, further cause the secondary hardware unit to process the first result received from the primary hardware unit prior to comparison of the first result to the second result by the comparator.

18. One or more machine-readable storage media comprising a plurality of instructions stored thereon that, when executed, cause a secondary hardware unit of an electrical system of an electrical device to:

receive data from a data bus, wherein the data is also provided to a primary hardware unit of the electrical system;

store the data in a set of data registers of the secondary hardware unit;

receive, from the primary hardware unit, a first result generated by the primary hardware unit by performance of a function on the data stored in a set of data registers of the primary hardware unit;

perform the function using the data stored in the set of data registers of the secondary hardware unit to generate a second result;

determine whether to perform a comparison of the first result and the second result; and

control, in response to a determination to perform the comparison, a comparator of the secondary hardware unit to perform the comparison of the first result and the second result.

19. The one or more machine-readable storage media of claim 18, wherein to determine whether to perform the comparison comprises to determine whether to perform the comparison based on a criteria and to provide an enable signal to the comparator to cause the comparator to perform the comparison in response to a determination that the perform the comparison.

20. The one or more machine-readable storage media of claim 19, wherein to determine whether to perform the comparison comprises to determine whether to perform the comparison based on an elapsed time since a reference point in time.

21. The one or more machine-readable storage media of claim 29, wherein to determine whether to perform the comparison comprises to determine whether to perform the comparison based on an analysis of data stored in the set of second data registers.

22. The one or more machine-readable storage media of claim 21, wherein to determine whether to perform the comparison comprises to determine whether to perform the comparison based on an elapsed time since data was written to the second set of data registers.