EXECUTING AN APPLICATION WITH MULTIPLE PROCESSORS

• US 20190324790A1
• Filed: 12/16/2016
• Published: 10/24/2019
• Est. Priority Date: 12/16/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Li, Tianyou, Xu, Shu, Ren, Jinkui, Jiang, Zidong, Lin, Weiliang, Zhu, Chaobo, Hu, Yong
• Granted Patent: US 11,099,879 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2009/45562 Creating, deleting, cloning virtual machine instances
• CPC Class Codes: G06F 2009/45575 Starting, stopping, suspending or resuming virtual machine instances
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

In one example, a system for executing applications can include a main processor to initialize a virtual machine to execute an application. The main processor can also determine a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture. Additionally, the main processor can transmit an instruction from the application to the auxiliary processor for execution and update context data for the application in response to receiving an execution result from the auxiliary processor.

Claims

1-22. -22. (canceled)

23. A system for executing applications comprising:

a main processor based on a main instruction set architecture, wherein the main processor is to;

initialize a virtual machine to execute an application;

determine a main utilization indicator of the main processor is above a first threshold and an auxiliary utilization indicator of an auxiliary processor is below a second threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture;

transmit an instruction from the application to the auxiliary processor for execution; and

update context data for the application in response to receiving an execution result from the auxiliary processor.

24. The system of claim 23, wherein the context data comprises a stack, a heap, or a virtual register.

25. The system of claim 23, wherein the main utilization indicator and the auxiliary utilization indicator are based on performance characteristics of the main processor and the auxiliary processor.

26. The system of claim 25, wherein the performance characteristics comprise a processor utilization value, a memory utilization value, and a free memory space value.

27. The system of claim 23, wherein the main processor is to execute an instruction for a second application in response to transmitting the instruction for the application to the auxiliary processor.

28. The system of claim 23, wherein the main processor is to detect that the instruction resides in memory shared between the main processor and the auxiliary processor, and transmit a pointer to the instruction to the auxiliary processor.

29. The system of claim 28, wherein the instruction comprises bytecode.

30. A system for executing applications comprising:

an auxiliary processor based on an auxiliary instruction set architecture, wherein the auxiliary processor to;

initialize a virtual machine to execute an application;

detect an instruction from a main processor to be executed by the auxiliary processor;

execute the instruction on the auxiliary processor with the auxiliary instruction set architecture; and

transmit context data corresponding to the execution of the instruction to the main processor.

31. The system of claim 30, wherein the auxiliary processor is to poll for the instruction from the main processor.

32. The system of claim 30, wherein the auxiliary processor is to detect an interrupt corresponding to the instruction from the main processor.

33. The system of claim 30, wherein the context data comprises a stack, a heap, or a virtual register.

34. The system of claim 30, wherein the instruction comprises bytecode.

35. A method for executing applications comprising:

initializing, via a main processor, a virtual machine to execute an application;

determining, via the main processor, a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture and the main processor is based on a main instruction set architecture, and wherein the auxiliary instruction set architecture is different from the main instruction set architecture;

transmitting, via the main processor, an instruction from the application to the auxiliary processor for execution; and

updating, via the main processor, context data for the application in response to receiving an execution result from the auxiliary processor.

36. The method of claim 35, wherein the context data comprises a stack, a heap, or a virtual register.

37. The method of claim 35, wherein the main utilization indicator and the auxiliary utilization indicator are based on performance characteristics of the main processor and the auxiliary processor.

38. The method of claim 35, wherein the performance characteristics comprise a processor utilization value, a memory utilization value, and a free memory space value.

39. The method of claim 35 comprising executing an instruction for a second application in response to transmitting the instruction for the application to the auxiliary processor.

40. The method of claim 35 comprising detecting that the instruction resides in memory shared between the main processor and the auxiliary processor, and transmitting a pointer to the instruction to the auxiliary processor.

41. A non-transitory computer-readable medium for executing applications comprising a plurality of instructions that in response to being executed by a main processor, cause the main processor to:

initialize, via the main processor, a virtual machine to execute an application;

determine, via the main processor, a main utilization indicator of the main processor is above a threshold and an auxiliary utilization indicator of an auxiliary processor is below a threshold, wherein the auxiliary processor is based on an auxiliary instruction set architecture and the main processor is based on a main instruction set architecture, and wherein the auxiliary instruction set architecture is different from the main instruction set architecture;

transmit, via the main processor, an instruction from the application to the auxiliary processor for execution; and

update, via the main processor, context data for the application in response to receiving an execution result from the auxiliary processor.

42. The non-transitory computer-readable medium of claim 41, wherein the context data comprises a stack, a heap, or a virtual register.

43. The non-transitory computer-readable medium of claim 41, wherein the main utilization indicator and the auxiliary utilization indicator are based on performance characteristics of the main processor and the auxiliary processor.

44. The non-transitory computer-readable medium of claim 41, wherein the plurality of instructions cause the main processor to detect that the instruction is bytecode that resides in memory shared between the main processor and the auxiliary processor, and transmit a pointer to the instruction to the auxiliary processor.