SOFTWARE DEFINED MULTI-DOMAIN CREATION AND ISOLATION FOR A HETEROGENEOUS SYSTEM-ON-CHIP

• US 20190324806A1
• Filed: 04/18/2018
• Published: 10/24/2019
• Est. Priority Date: 04/18/2018
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Javre, Somdutt, Rele, Siddharth, Budde, Gangadhar, Nali, Appa Rao, Kamarapu, Chaitanya
• Granted Patent: US 10,853,134 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 8/20 Software design
• CPC Class Codes: G06F 8/30 Creation or generation of source code
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources

Abstract

Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

Claims

1. A method, comprising:

receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous System-on-Chip (SoC);

creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources;

assigning, using the computer hardware, an operating system to each domain; and

generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

2. The method of claim 1, wherein the platform includes configuration data for configuring isolation circuits of the heterogeneous SoC.

3. The method of claim 1, wherein the platform includes a first stage boot loader configured to initialize a processor system of the heterogeneous SoC.

4. The method of claim 1, wherein the platform includes, for a selected domain of the plurality of domains, a device tree for the operating system assigned to the selected domain, wherein the device tree is generated based upon the hardware resource selected from the plurality of hardware resources.

5. The method of claim 1, wherein each domain is logically enforced within the heterogeneous SoC.

6. The method of claim 1, further comprising:

modifying at least one domain of the plurality of domains for the heterogeneous SoC using the hardware description file.

7. The method of claim 1, wherein the platform includes a plurality of artifacts for the plurality of domains for use by a software development environment, the method further comprising:

generating executable program code for a selected domain of the plurality of domains using an artifact selected from the plurality of artifacts that corresponds to the selected domain.

8. The method of claim 1, wherein each domain is assigned a portion of available random-access memory.

9. A system, comprising:

a memory configured to store program code; and

a processor coupled to the memory, wherein the processor, in response to executing the program code, is configured to initiate operations including;

receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous System-on-Chip (SoC);

creating a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources;

assigning an operating system to each domain; and

generating a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

10. The system of claim 9, wherein the platform includes configuration data for configuring isolation circuits of the heterogeneous SoC.

11. The system of claim 9, wherein the platform includes a first stage boot loader configured to initialize a processor system of the heterogeneous SoC.

12. The system of claim 9, wherein the platform includes, for a selected domain of the plurality of domains, a device tree for the operating system assigned to the selected domain, wherein the device tree is generated based upon the hardware resource selected from the plurality of hardware resources.

13. The system of claim 9, wherein each domain is logically enforced within the heterogeneous SoC.

14. The system of claim 9, wherein the processor is configured to initiate operations further comprising:

modifying at least one domain of the plurality of domains for the heterogeneous SoC using the hardware description file.

15. The system of claim 9, wherein the platform includes a plurality of artifacts for the plurality of domains for use by a software development environment, wherein the processor is configured to initiate operations further comprising:

generating executable program code for a selected domain of the plurality of domains using an artifact selected from the plurality of artifacts that corresponds to the selected domain.

16. The system of claim 9, wherein each domain is assigned a portion of available random-access memory.

17. A computer program product, comprising:

a computer readable storage medium having program code stored thereon, the program code executable by computer hardware to initiate operations including;

receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous System-on-Chip (SoC);

creating a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources;

assigning an operating system to each domain; and

generating a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

18. The computer program product of claim 17, wherein the platform includes configuration data for configuring isolation circuits of the heterogeneous SoC.

19. The computer program product of claim 17, wherein the platform includes a first stage boot loader configured to initialize a processor system of the heterogeneous SoC.

20. The computer program product of claim 17, wherein the platform includes, for a selected domain of the plurality of domains, a device tree for the operating system assigned to the selected domain, wherein the device tree is generated based upon the hardware resource selected from the plurality of hardware resources.