SYSTEM AND METHOD FOR EVENT MONITORING IN CACHE COHERENCE PROTOCOLS WITHOUT EXPLICIT INVALIDATIONS
First Claim
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1. A computer system comprising:
- multiple processor cores;
at least one local cache memory associated with and operatively coupled to each core for storing one or more cache lines accessible only by the associated core;
a shared memory, the shared memory being operatively coupled to the local cache memories and accessible by the cores, the shared memory being capable of storing a plurality of cache lines; and
wherein a core issuing a callback-read to a memory address either reads the last value written in the memory address or is blocked from reading the memory address until the next write takes place in the memory address and then reads a new value of said next write such that the callback-read enables event monitoring for coherence of the at least one local cache and the shared memory without using explicit invalidations.
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Abstract
Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.
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38 Claims
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1. A computer system comprising:
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multiple processor cores; at least one local cache memory associated with and operatively coupled to each core for storing one or more cache lines accessible only by the associated core; a shared memory, the shared memory being operatively coupled to the local cache memories and accessible by the cores, the shared memory being capable of storing a plurality of cache lines; and wherein a core issuing a callback-read to a memory address either reads the last value written in the memory address or is blocked from reading the memory address until the next write takes place in the memory address and then reads a new value of said next write such that the callback-read enables event monitoring for coherence of the at least one local cache and the shared memory without using explicit invalidations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 22, 31)
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20. A method comprising:
monitoring synchronization events associated with cache coherence without using explicit invalidations by issuing a callback-read to a memory address, which callback-read either enables a processor core to read the last value written in the memory address, or blocks the processor core from reading the memory address until a next write takes place in the memory address and read a newly written value of said next write. - View Dependent Claims (21, 23, 24, 25, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 37, 38)
Specification