SERIAL PERIPHERAL INTERFACE FILTER FOR PROCESSOR SECURITY

• US 20190324923A1
• Filed: 04/20/2018
• Published: 10/24/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: KELLY, Bryan David, WEIMER, Christopher Lawrence, SHAW, Mark Andrew, RAGHU, Priya
• Granted Patent: US 10,740,252 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 2212/1052 Security improvement

Abstract

A processor may be coupled to a flash memory by way of an interface. The processor may be caused to read and/or write data, such as computer executable instructions, from/to the flash memory via the interface. An interface filter may be interposed between the processor and the flash memory to enhance the security and validity of data transactions associated with the processor and the flash memory.

Claims

1. An apparatus, comprising:

a processor;

a memory component coupled to the processor;

a serial peripheral interface (SPI) coupling the processor and the memory component, the SPI providing at least a chip select (CS) line and at least one data line; and

a filter device coupled to the CS line and the at least one data line, the filter device to;

analyze an instruction on the at least one data line, and

interrupt a signal on the CS line in response to the analysis of the instruction on the at least one data line.

2. The apparatus according to claim 1, wherein the instruction comprises at least a command and an address, the filter device to analyze at least one of the command and the address and interrupt the signal when the analysis of at least one of the command and the address indicates that at least one of the command and the address is invalid or poses a security threat to at least one of the processor and the memory component.

3. The apparatus according to claim 1, wherein the signal is at a logic level low prior to the analysis of the instruction, the filter device to interrupt the signal by causing the signal to transition to a logic level high in response to the analysis of the instruction.

4. The apparatus according to claim 1, wherein the instruction comprises at least an address having an associated plurality of bits representing an address location of the memory component, the filter device to analyze the associated plurality of bits and interrupt the signal when the analysis of the associated plurality of bits indicates that the address is improper or poses a security threat to at least one of the processor and the memory component, the filter device to interrupt the signal before a final bit of the plurality of bits is communicated to the memory component.

5. The apparatus according to claim 4, wherein interrupting the signal causes formation of a corrupt instruction on the at least one data line, the memory component functional to ignore or discard corrupt instructions received thereby.

6. The apparatus according to claim 1, wherein the memory component is a flash memory comprising at least a portion of memory reserved for read only access, the instruction comprising a write command and an address associated with at least a portion of the memory reserved for read only access, the analysis of the instruction causing the filter device to:

detect that the write command is linked to the address, and

interrupt the signal, in response to detecting that the write command is linked to the address.

7. The apparatus according to claim 1, wherein the memory component is a flash memory comprising at least a portion of memory reserved for read only access, the instruction comprising an address associated with at least a portion of the memory reserved for read only access and data to be written to at least a portion of the memory reserved for read only access, the analysis of the instruction causing the filter device to:

determine that the data is to be written to at least a portion of the memory reserved for read only access, and

interrupt the signal in response to determining that the data is to be written to at least a portion of the memory reserved for read only access.

8. The apparatus according to claim 1, wherein the filter device coupled to the CS line and a plurality of data lines, and the instruction is on one or more of the plurality of data lines, the filter device to analyze the instruction and interrupt the signal in response to the analysis of the instruction.

9. An apparatus, comprising:

a master component;

a slave component coupled to the master component;

an interface coupling the master component and the slave component, the interface providing at least a slave select (SS) line and at least one data line, the SS line including a signal generated by the master component to select the slave component, and the at least one data line including an instruction for communication to the slave component; and

a processor device coupled to the SS line and the at least one data line, the processor device to;

analyze the instruction, and

interrupt the signal on the SS line in response to the analysis of the instruction.

10. The apparatus according to claim 9, wherein the master component is a processor, the slave component is a flash memory and the interface is a serial peripheral interface (SPI).

11. The apparatus according to claim 9, wherein the instruction comprises at least a command and an address, the processor device to analyze at least one of the command and the address and interrupt the signal when the analysis of at least one of the command and the address indicates that at least one of the command and the address is invalid or poses a security threat to at least one of the master component and the slave component.

12. The apparatus according to claim 9, wherein the signal is at a logic level low prior to the analysis of the instruction on the at least one data line, the filter device to interrupt the signal by causing the signal to transition to a logic level high in response to the analysis of the instruction.

13. The apparatus according to claim 9, wherein the instruction comprises at least an address having an associated plurality of bits representing an address location of the slave component, the processor device to analyze the associated plurality of bits and interrupt the signal when the analysis of the associated plurality of bits indicates that the address is improper or poses a security threat to at least one of the master component and the slave component, the processor device to interrupt the signal before a final bit of the plurality of bits is communicated to the slave component.

14. The apparatus according to claim 13, wherein interrupting the signal causes formation of a corrupt instruction on the at least one data line, the slave component functional to ignore or discard corrupt instructions received thereby.

15. An apparatus, comprising:

a processor comprising at least one data output and a chip select (CS) output;

a first flash memory component and a second flash memory component, each of the first flash memory component and the second flash memory component comprising a CS input, the first and second flash memory components coupled to the at least one data output; and

a filter device comprising a CS input and first and second CS outputs, the CS input coupled to the CS output of the processor, the first CS output coupled to the CS input of the first flash memory component and the second CS output coupled to the CS input of the second flash memory component.

16. The apparatus according to claim 15, wherein the filter device comprises at least one data input coupled to the at least one data output, the processor to provide an instruction on the at least one data output, the filter device to

analyze the instruction via the at least one data input, and

interrupt a signal on the first CS output or the second CS output in response to the analysis of the instruction.

17. The apparatus according to claim 16, wherein the instruction comprises at least a command and an address, the filter device to analyze at least one of the command and the address and interrupt the signal on the first CS output or the second CS output when the analysis of at least one of the command and the address indicates that at least one of the command and the address is invalid or poses a security threat to at least one of the processor, the first flash memory component and second flash memory component.

18. The apparatus according to claim 16, wherein the signal on the first CS output or the second CS output is at a logic level low prior to the analysis of the instruction, the filter device to interrupt the signal on the first CS output or the second CS output by causing the signal to transition to a logic level high in response to the analysis of the instruction.

19. The apparatus according to claim 16, wherein the instruction comprises at least an address having an associated plurality of bits representing an address location, the filter device to analyze the associated plurality of bits and interrupt the signal on the first CS output or the second CS output when the analysis of the associated plurality of bits indicates that the address is improper or poses a security threat to at least one of the processor, the first flash memory component and second flash memory component, the filter device to interrupt the signal before a final bit of the plurality of bits is communicated to the first flash memory component or second flash memory component.

20. The apparatus according to claim 16, wherein the at least one data output and the CS output are associated with a serial peripheral interface (SPI) linked to the processor.