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SERIAL PERIPHERAL INTERFACE FILTER FOR PROCESSOR SECURITY

  • US 20190324923A1
  • Filed: 04/20/2018
  • Published: 10/24/2019
  • Est. Priority Date: 04/20/2018
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a processor;

    a memory component coupled to the processor;

    a serial peripheral interface (SPI) coupling the processor and the memory component, the SPI providing at least a chip select (CS) line and at least one data line; and

    a filter device coupled to the CS line and the at least one data line, the filter device to;

    analyze an instruction on the at least one data line, andinterrupt a signal on the CS line in response to the analysis of the instruction on the at least one data line.

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