SYSTEM AND METHOD FOR PORT-TO-PORT COMMUNICATIONS USING DIRECT MEMORY ACCESS

• US 20190324926A1
• Filed: 04/19/2018
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Wu, Kenny, Karnowski, Mark, Smart, James, Shenoy, Ravi, Chhabra, Lalit, Gervasio, JR., Gregorio, Le, Tuong, Nguyen, Vuong
• Granted Patent: US 10,664,420 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.

Claims

1. A system that facilitates chip-to-chip transport of header descriptors and payloads, comprising:

a source chip;

a destination chip;

a set of queues describing buffer memory locations for staging the header descriptors and payloads to be transferred from the source chip to the destination chip, wherein the set of queues are directly accessible to the source chip and to the destination chip; and

a host device that executes a setup routine to configure the set of queues to facilitate information transfers between the source chip and the destination chip, wherein the information transfers bypass the host device after the set of queues have been configured by the host device.

2. The system of claim 1, wherein the set of queues comprises a work queue (WQ), receive queue (RQ) pair, header buffer and payload buffer.

3. The system of claim 2, wherein a queue depth of the WQ and RQ pair is equal.

4. The system of claim 2, wherein the set of queues comprises the payload buffer and the header buffer, wherein an RQ payload contains payload buffer memory addresses where payloads are placed by the source chip, and wherein an RQ header contains header buffer memory addresses where a work queue entry (WQE) is created by the source chip with a header descriptor that provides information on a corresponding payload.

5. The system of claim 4, wherein the information provided in the header descriptor comprises at least one of frame header, optional header, and control attributes.

6. The system of claim 4, wherein the source chip maintains a phase state bit that tracks a state of a current valid phase and wherein the phase state bit is toggled when the WQ wraps to a predetermined index.

7. The system of claim 1, wherein the source chip rings a work queue (WQ) doorbell with a WQ identifier to the destination chip via a PCIe posted memory write transaction once data placements into the buffer memory locations are complete.

8. The system of claim 1, wherein the buffer memory locations are maintained at the destination chip.

9. The system of claim 1, wherein the buffer memory locations are accessed by the source chip through a network fabric.

10. The system of claim 9, wherein the network fabric comprises a PCIe network fabric, wherein the source chip writes the header descriptors and payloads directly to the buffer memory locations without assistance from a host, and wherein the destination chip retrieves the header descriptors and payloads directly from the buffer memory locations.

11. The system of claim 1, wherein the buffer memory locations are co-located with one or both of the source chip and destination chip.

12. A method of enabling chip-to-chip transport of header descriptors and payloads, the method comprising:

establishing, with a host device, a set of queues that describe memory locations in non-host memory for staging the header descriptors and payloads to be transferred from a source chip to a destination chip;

enabling the source chip to directly write information into buffer memory locations described by the set of queues while bypassing the host device; and

enabling the destination chip to directly read the information from the buffer memory locations described by the set of queues while bypassing the host device.

13. The method of claim 12, wherein the set of queues comprises a work queue (WQ), receive queue (RQ) pair, header buffer and payload buffer, wherein a queue depth of the WQ and RQ pair is equal, wherein the set of queues comprises the payload buffer and the header buffer, wherein an RQ payload contains payload buffer memory addresses where payloads are placed by the source chip, and wherein an RQ header contains header buffer memory addresses where a work queue entry (WQE) is created by the source chip with a header descriptor that provides information on a corresponding payload.

14. The method of claim 13, further comprising:

maintaining a phase state bit that tracks a state of a current valid phase; and

toggling the phase state bit when the WQ wraps to a predetermined index.

15. The method of claim 12, wherein the source chip rings a work queue (WQ) doorbell with a WQ identifier to the destination chip via a PCIe posted memory write transaction once data placements into the buffer memory locations are complete.

16. The method of claim 12, wherein the buffer memory locations are accessed by the source chip through a network fabric.

17. An adaptor, comprising:

a data source;

a data destination;

buffer memory; and

a set of queues describing buffer memory locations in the buffer memory, wherein the set of queues are setup by a host device to facilitate information transfers between the data source and the data destination while bypassing the host device, wherein the buffer memory provides a location for staging header descriptors and payloads to be transferred from the data source to the data destination.

18. The adaptor of claim 17, wherein the set of queues comprises a work queue (WQ), receive queue (RQ) pair, wherein a queue depth of the WQ and RQ pair is equal, wherein the set of queues comprises a payload buffer and a header buffer, wherein an RQ payload contains payload buffer memory addresses where the payloads are placed by the data source, and wherein an RQ header contains header buffer memory addresses where a work queue entry (WQE) is created by the data source with a header descriptor that provides information on a corresponding payload.

19. The adaptor of claim 17, wherein the data source rings a work queue (WQ) doorbell with a WQ identifier to the data destination.

20. The adaptor of claim 17, wherein the data source comprises a first port of the adaptor and wherein the data destination comprises a second port of the adaptor.