VIRTUALIZATION IN HIERARCHICAL CORTICAL EMULATION FRAMEWORKS

• US 20190324929A1
• Filed: 04/23/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kumar, Arvind, Ozcan, Ahmet S., Scott, J. Campbell
• Granted Patent: US 11,163,707 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent

Abstract

Embodiments of the present invention describe a hierarchical cortical emulation using a scratchpad memory device and a storage class memory device. The scratchpad memory device is partitioned into a first subset of memory locations and a second subset of memory locations. A processor from a neural network device is assigned a first memory portion from the first subset, a second memory portion from the second subset, and a third memory portion from the storage class memory device. Further the neural network device and a memory controller perform a compute cycle for a hierarchical level k, 1≤k≤n, n being total number of levels. A compute cycle includes performing, by the processor, computations from the level k using neuron data stored in the first memory portion, and in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

Claims

1. A hierarchical cortical emulation system comprising:

a neural network device comprising a plurality of processors;

a memory controller communicatively coupled with the neural network device;

a scratchpad memory device communicatively coupled to the memory controller; and

a storage class memory device communicatively coupled to the memory controller;

wherein;

the scratchpad memory device is partitioned into a first subset of memory locations and a second subset of memory locations;

a processor from the plurality of processors of the neural network device is assigned a first memory portion from the first subset of memory locations, a second memory portion from the second subset of memory locations, and a third memory portion from the storage class memory device; and

the neural network device and the memory controller perform a compute cycle for a hierarchical level k from the hierarchical cortical emulation that contains n levels, 1≤

k≤

n, wherein the compute cycle comprises;

performing, by the processor, computations for a neuron from the level k using neuron data for the hierarchical level k stored in the first memory portion; and

in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

2. The system of claim 1, wherein the first memory portion is used to store the neuron data for odd numbered hierarchical levels and the second memory portion is used to store the neuron data for even numbered hierarchical levels.

3. The system of claim 1, wherein copying the neuron data for level k+1 comprises selecting, from the third memory portion the neuron data for level k+1 from the neuron data for all hierarchical levels.

4. The system of claim 1, wherein performing the compute cycle k further comprises updating the neuron data for one or more neurons from the hierarchical level k in the storage class memory device.

5. The system of claim 4, wherein the memory controller updates the neuron data by performing one or more mathematical computations on the neuron data that is stored in the storage class memory device.

6. The system of claim 1, wherein the neuron from the hierarchical level k is a first neuron, and wherein the neural network device and the memory controller perform a compute cycle k+1 for the hierarchical level k+1 from the hierarchical cortical emulation, in which the same processor performs computations for a second neuron from the hierarchical level k+1 using the neuron data for the hierarchical level k+1 stored in the second memory portion.

7. The system of claim 1, wherein the processor performs computations for a plurality of neurons from the hierarchical level k.

8. A computer-implemented method comprising:

partitioning, by a memory controller, a scratchpad memory device into a first subset of memory locations and a second subset of memory locations;

assigning, by a controller, a processor, from a plurality of processors of a neural network device, a first memory portion from the first subset of memory locations, a second memory portion from the second subset of memory locations, and a third memory portion from a storage class memory device; and

performing, by the neural network device and the memory controller, a compute cycle k for a hierarchical level k from a hierarchical cortical emulation that contains n levels, 1≤

k≤

n, wherein the compute cycle k comprises;

performing, by the processor, computations for a neuron from the hierarchical level k using neuron data for the hierarchical level k stored in the first memory portion; and

in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

9. The computer-implemented method of claim 8, wherein the first memory portion is used to store the neuron data for odd numbered hierarchical levels and the second memory portion is used to store the neuron data for even numbered hierarchical levels.

10. The computer-implemented method of claim 8, wherein copying the neuron data for the hierarchical level k+1 comprises selecting, from the third memory portion the neuron data for the hierarchical level k+1 from the neuron data for all hierarchical levels.

11. The computer-implemented method of claim 8, wherein performing the compute cycle k further comprises updating the neuron data for one or more neurons from the hierarchical level k in the storage class memory device.

12. The computer-implemented method of claim 11, wherein the memory controller updates the neuron data by performing one or more mathematical computations on the neuron data that is stored in the storage class memory device.

13. The computer-implemented method of claim 8, wherein the neuron from the hierarchical level k is a first neuron, and wherein the neural network device and the memory controller perform a compute cycle k+1 for the hierarchical level k+1 from the hierarchical cortical emulation, in which the same processor performs computations for a second neuron from the hierarchical level k+1 using the neuron data for the hierarchical level k+1 stored in the second memory portion.

14. The computer-implemented method of claim 8, wherein the processor performs computations for a plurality of neurons from the hierarchical level k.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing circuit to cause the processing circuit to perform a hierarchical cortical emulation comprising:

partitioning a scratchpad memory device into a first subset of memory locations and a second subset of memory locations;

assigning a processor, from a plurality of processors of a neural network device, a first memory portion from the first subset of memory locations, a second memory portion from the second subset of memory locations, and a third memory portion from a storage class memory device; and

performing, by the neural network device and a memory controller, a compute cycle k for a hierarchical level k from a hierarchical cortical emulation that contains n levels, 1≤

k≤

n, wherein the compute cycle k comprises;

performing, by the processor, computations for a neuron from the hierarchical level k using neuron data for the hierarchical level k stored in the first memory portion; and

in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

16. The computer program product of claim 15, wherein the first memory portion is used to store the neuron data for odd numbered hierarchical levels and the second memory portion is used to store the neuron data for even numbered hierarchical levels.

17. The computer program product of claim 15, wherein copying the neuron data for the hierarchical level k+1 comprises selecting, from the third memory portion the neuron data for the hierarchical level k+1 from the neuron data for all hierarchical levels.

18. The computer program product of claim 15, wherein performing the compute cycle k further comprises updating the neuron data for one or more neurons from the hierarchical level k in the storage class memory device.

19. The computer program product of claim 15, wherein the neuron from the hierarchical level k is a first neuron, and wherein the neural network device and the memory controller perform a compute cycle k+1 for the hierarchical level k+1 from the hierarchical cortical emulation, in which the same processor performs computations for a second neuron from the hierarchical level k+1 using the neuron data for the hierarchical level k+1 stored in the second memory portion.

20. The computer program product of claim 15, wherein the processor performs computations for a plurality of neurons from the hierarchical level k.