Machine learning based post route path delay estimator from synthesis netlist
First Claim
1. A device for generation a circuit fabrication structure, the device comprising:
- neural network logic, comprisingan embedding layer to;
receive a gate function vector and an embedding width; and
alter a shape of the gate function vector by the embedding width;
a concatenator to;
receive a gate feature input vector; and
concatenate the gate feature input vector with the gate function vector altered by the embedding width;
a convolution layer to;
receive a window size, stride, and output feature size; and
generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer;
a fully connected layer to reduce the output convolution vector to a final circuit path delay output; and
logic to utilize the final circuit delay output in a circuit fabrication structure.
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Abstract
A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.
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Citations
17 Claims
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1. A device for generation a circuit fabrication structure, the device comprising:
neural network logic, comprising an embedding layer to; receive a gate function vector and an embedding width; and alter a shape of the gate function vector by the embedding width; a concatenator to; receive a gate feature input vector; and concatenate the gate feature input vector with the gate function vector altered by the embedding width; a convolution layer to; receive a window size, stride, and output feature size; and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer; a fully connected layer to reduce the output convolution vector to a final circuit path delay output; and logic to utilize the final circuit delay output in a circuit fabrication structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
Specification