METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

• US 20190325104A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 09/10/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LUM, Annie, TAO, Derek C., LEE, Cheng Hung, LU, Chung-Ji, CHENG, Hong-Chen, AGRAWAL, Vineet Kumar, KIM, Keun-Young, CHO, Pyong Yun
• Granted Patent: US 10,762,269 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Claims

1. A method, comprising:

designing a first layout including gate structures and diffusion regions of a plurality of active devices;

identifying an edge device of the plurality of active devices;

modifying the first layout resulting in a second layout comprising;

adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region;

adding a dummy gate structure next to the dummy device; and

extending the shared diffusion region to at least the dummy device;

performing a design rule check on the second layout, the performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device; and

fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device.

2. The method of claim 1, wherein extending the shared diffusion region to at least the dummy device comprises:

extending the shared diffusion region to at least a first side of the dummy device, the first side of the dummy device being closer to the edge device than a second side of the dummy device.

3. The method of claim 1, wherein modifying the first layout resulting in the second layout further comprises:

adding an additional diffusion region on a side of the dummy device opposite from the edge device.

4. The method of claim 3, wherein a length of the additional diffusion region is less than a length of the shared diffusion region.

5. The method of claim 4, wherein the length of the additional diffusion region is equal to a length of another diffusion region on a side of the edge device opposite from the dummy device.

6. The method of claim 1, wherein the gate structure of the dummy device has a first gate length and the gate structure of the edge device has a second gate length different from the first gate length.

7. The method of claim 6, wherein the dummy gate structure has a gate length equal to the first gate length or the second gate length.

8. The method of claim 1, further comprising deactivating the dummy device.

9. The method of claim 1, further comprising:

removing at least one dummy gate structure, so that the dummy gate structure corresponds to a single dummy gate structure next to the dummy device.

10. A method, comprising:

designing a first layout including gate structures and diffusion regions of a semiconductor device;

identifying neighboring gate structures having different gate lengths, the neighboring gate structures including a first gate structure having a first gate length and a second gate structure having a second gate length different from the first gate length;

modifying the first layout resulting in a second layout comprising;

inserting a dummy device between the first gate structure and the second gate structure; and

extending a first diffusion region of the first gate structure to the dummy device, the first diffusion region being shared by the dummy device and the first gate structure;

performing a design rule check on the second layout, the performing the design rule check comprises considering the sharing of the first diffusion region by the dummy device and the first gate structure as complying with a design rule of the design rule check; and

fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of the semiconductor device.

11. The method of claim 10, further comprising:

extending a second diffusion region of the second gate structure to the dummy device, the second diffusion region being shared by the dummy device and the second gate structure, and the first diffusion region and the second diffusion region having different widths.

13. The method of claim 10, further comprising:

adding another diffusion region between the dummy device and a second diffusion region of the second gate structure, the second diffusion region and the another diffusion region being shared by the dummy device and the second gate structure, and the first diffusion region and the another diffusion region having a same width.

14. The method of claim 13, wherein performing the design rule check on the second layout further comprises:

considering the sharing of the second diffusion region and the another diffusion region by the dummy device and the second gate structure as complying with the design rule of the design rule check.

15. The method of claim 10, further comprising deactivating the dummy device.

16. The method of claim 10, wherein the dummy device has one of the first gate length or the second gate length.

19. The method of claim 15, further comprising:

extending the first diffusion region of the first gate structure to at least a first side of the dummy device; and

adding an additional diffusion region between the second diffusion region of the second gate structure and a second side of the dummy device,

wherein the additional diffusion region adjacent to the second side of the dummy device is different from the second diffusion region of the second gate structure.

12. The method of claim 12, wherein performing the design rule check on the second layout further comprises:

considering the sharing of the second diffusion region by the dummy device and the second gate structure as complying with the design rule of the design rule check.

17. A method, comprising:

designing a first layout of gate structures and diffusion regions for a semiconductor device;

identifying a first device having a first gate structure and an irregular diffusion region adjacent to a second device having a second gate structure and a diffusion region different from the irregular diffusion region;

inserting a dummy device between the first gate structure and the second gate structure resulting in a second layout, wherein a first diffusion region is shared by the dummy device and the first gate structure, a second diffusion region is shared by the dummy device and the second gate structure, the first diffusion region or the second diffusion region has a rectangular shape, and the irregular diffusion region has a non-rectangular shape;

performing a design rule check on the second layout, the performing the design rule check comprises considering the sharing of the first diffusion region by the dummy device and the first gate structure or the sharing of the second diffusion region by the dummy device and the second gate structure as complying with a design rule of the design rule check; and

fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of the semiconductor device.

18. The method of claim 17, further comprising:

extending the first diffusion region of the first gate structure to the dummy device; and

extending the second diffusion region of the second gate structure to the dummy device.

20. The method of claim 17, further comprising deactivating the dummy device.