APPARATUS FOR EXECUTING LSTM NEURAL NETWORK OPERATION, AND OPERATIONAL METHOD

• US 20190325298A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 12/30/2016
• Status: Active Grant

• Current Assignee: Shanghai Cambricon Information Technology Co., Ltd.
• Original Assignee: Sanghai Cambricon Information Technology Company Limited
• Inventors: CHEN, Yunji, CHEN, Xiaobing, LIU, Shaoli, CHEN, Tianshi
• Granted Patent: US 10,853,722 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06N 3/044 Recurrent networks, e.g. Hopfield networks
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

Aspects of processing data for Long Short-Term Memory (LSTM) neural networks are described herein. The aspects may include one or more data buffer units configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values. The aspects may further include multiple data processing units configured to parallelly calculate a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.

Claims

1. A Long Short-Term Memory (LSTM) neural network processor, comprising:

one or more data buffer units configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values; and

multiple data processing units configured to parallelly calculate a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.

2. The neural network processor of claim 1,

wherein the weight values include:

one or more forget gate weight values corresponding to a forget gate,

one or more input gate weight values corresponding to an input gate,

one or more candidate weight values corresponding to an updated state cell, and

one or more output gate weight values corresponding to an output gate, and

wherein the bias values include;

one or more forget gate bias values corresponding to the forget gate,

one or more input gate bias values corresponding to the input gate,

one or more candidate bias values corresponding to the candidate state value, and

one or more output gate bias values corresponding to the output gate.

3. The neural network processor of claim 2, wherein the multiple data processing units are configured to parallelly calculate a portion of a forget gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more forget gate weight values, the one or more forget gate bias values.

4. The neural network processor of claim 3, wherein the multiple data processing units are configured to parallelly calculate a portion of an input gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more input gate weight values, and the one or more input gate bias values.

5. The neural network processor of claim 4, wherein the multiple data processing units are configured to parallelly calculate a portion of a candidate state value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more candidate weight values, and the one or more candidate bias values.

6. The neural network processor of claim 5, wherein the multiple data processing units are configured to parallelly calculate a portion of an output gate value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more output gate weight values, and the one or more output gate bias values.

7. The neural network processor of claim 6, wherein the multiple data processing units are configured to parallelly calculate a current state value at the current timepoint based on a previous state value at the previous timepoint, the candidate state value, the forget gate output, and the input gate output.

8. The neural network processor of claim 7, wherein the multiple data processing units are configured to parallelly calculate the portion of the output value based on the output gate value and the current state value.

9. The neural network processor of claim 1, wherein each of the multiple data processing units includes one or more dot product processors, one or more vector adders, and one or more vector summation processors.

10. The neural network processor of claim 9, wherein the one or more dot product processors, one or more vector adders, and one or more vector summation processors are configured to parallelly calculate the portion of the output value at the current timepoint.

11. A method for processing data for Long Short-Term Memory (LSTM) neural networks, comprising:

storing, by one or more data buffer units, previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values; and

parallelly calculating, by multiple data processing units, a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.

12. The method of claim 11,

wherein the weight values include:

one or more forget gate weight values corresponding to a forget gate,

one or more input gate weight values corresponding to an input gate,

one or more candidate weight values corresponding to an updated state cell, and

one or more output gate weight values corresponding to an output gate, and

wherein the bias values include;

one or more forget gate bias values corresponding to the forget gate,

one or more input gate bias values corresponding to the input gate,

one or more candidate bias values corresponding to the candidate state value, and

one or more output gate bias values corresponding to the output gate.

13. The method of claim 12, further comprising parallelly calculating, by the multiple data processing units, a portion of a forget gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more forget gate weight values, the one or more forget gate bias values.

14. The method of claim 13, further comprising parallelly calculating, by the multiple data processing units, a portion of an input gate output based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more input gate weight values, and the one or more input gate bias values.

15. The method of claim 14, further comprising parallelly calculating, by the multiple data processing units, a portion of a candidate state value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more candidate weight values, and the one or more candidate bias values.

16. The method of claim 15, further comprising parallelly calculating, by the multiple data processing units, a portion of an output gate value based on the previous output data at the previous timepoint, the input data at the current timepoint, and the one or more output gate weight values, and the one or more output gate bias values.

17. The method of claim 16, further comprising parallelly calculating, by the multiple data processing units, a current state value at the current timepoint based on a previous state value at the previous timepoint, the candidate state value, the forget gate output, and the input gate output.

18. The method of claim 17, further comprising parallelly calculating, by the multiple data processing units, the portion of the output value based on the output gate value and the current state value.

19. The method of claim 11, wherein each of the multiple data processing units includes one or more dot product processors, one or more vector adders, and one or more vector summation processors.

20. The method of claim 19, further comprising parallelly calculating, by the one or more dot product processors, one or more vector adders, and one or more vector summation processors, the portion of the output value at the current timepoint.