NEURAL NETWORK CIRCUIT

• US 20190325311A1
• Filed: 01/10/2017
• Published: 10/24/2019
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: NAKAMURA, Toshiaki, HIROTSU, Teppei, HORIGUCHI, Tatsuya
• Granted Patent: US 11,531,896 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 17/11 for solving equations , e.g. nonlinear equations, general mathematical optimization problems optimization specially adapted for a specific administrative, business or logistic context G06Q10/04
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/082 modifying the architecture, e.g. adding, deleting or silencing nodes or connections

Abstract

The present invention addresses the problem of implementing a neural network using a small-scale circuit by simplifying the multiplication of the input data by weight data. The neural network circuit according to the present invention is configured from: a means for multiplying input data by a rounded value of the mantissa part of weight data; a means for shifting the multiplication result by the number of bits of the rounded value; a means for adding the shifted result to the original input data; and a means for shifting the addition result by the number of bits of the exponent part of the weight.

Claims

1. A neural network circuit comprising

a means for providing weight factors corresponding to a plurality of pieces of input data as each information indicating a weight rounded value and an amount of bit shift and performing a weighting operation on the input data by multiplication with the weight rounded value and the bit shift, in neurons constituting a neural network.

2. The neural network circuit according to claim 1, wherein

in the neurons constituting the neural network, a value after the weighting operation on the input data is a result of the multiplication with the weight rounded value and the bit shift.

3. The neural network circuit according to claim 1, wherein

a circuit on which the weight factors corresponding to the plurality of pieces of input data are mounted includes a means for converting the input data to the information indicating the weight rounded value and the amount of bit shift.

4. The neural network circuit according to claim 1, wherein

the weight factors, obtained by an operation in which the number of the weight factors is constant in a range between 2ⁿ and 2ⁿ⁻

1, are provided.

5. The neural network circuit according to claim 1, wherein

the weight factors, obtained by an operation in which the number of the weight factors is constant in a range between 2ⁿ and 0, are provided.

6. A neural network circuit comprising:

a means for multiplying input data by a rounded value of a mantissa part of weight data;

a means for shifting the multiplication result by the number of bits of the rounded value;

a means for adding the shifted result to the original input data; and

a means for shifting the addition result by the number of bits of an exponent part of the weight.