SYSTEM AND METHODS FOR EXTRACTION OF THRESHOLD AND MOBILITY PARAMETERS IN AMOLED DISPLAYS

• US 20190325798A1
• Filed: 04/30/2019
• Published: 10/24/2019
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Ngan, Ricky Yik Hei, Zahirovic, Nino, Azizi, Yaser
• Granted Patent: US 10,713,986 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2230/00 Details of flat display driving waveforms
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A system reads a desired circuit parameter from a pixel circuit that includes a light emitting device, a drive device to provide a programmable drive current to the light emitting device, a programming input, and a storage device to store a programming signal. One embodiment of the extraction system turns off the drive device and supplies a predetermined voltage from an external source to the light emitting device, discharges the light emitting device until the light emitting device turns off, and then reads the voltage on the light emitting device while that device is turned off. The voltages on the light emitting devices in a plurality of pixel circuits may be read via the same external line, at different times.

Claims

1-13. -13. (canceled)

14. A display comprising:

a first signal line for outputting an output signal;

a plurality of pixel circuits, each pixel circuit comprising;

a light emitting device;

a drive transistor for controlling current supplied to the light emitting device, said drive transistor having a gate terminal, a source terminal and a drain terminal;

a storage device coupled between the gate terminal of the drive transistor and one of the source terminal and the drain terminal of the drive transistor, a first node of the pixel circuit located between the storage device and the drive transistor;

a first switching transistor controllably coupling the first signal line to a second node of the pixel circuit located between the storage device and the one of the source terminal and the drain terminal of the drive transistor;

and

a controller coupled to each pixel circuit and configured to supply controlling input signals to the pixel circuit in a predetermined sequence to produce the output signal which is a function of a parameter of the pixel circuit, the sequence including;

i) supplying a first initial voltage to the first node;

ii) turning off the first switching transistor, and controlling the drive transistor so that current flows through the light emitting device and the drive transistor, the magnitude of said current being controlled by a gate voltage applied to the gate terminal of the drive transistor discharged by the storage device; and

iii) turning on the first switching transistor and extracting the parameter of the pixel circuit by reading the output signal over the first signal line.

15. The display according to claim 14, wherein the controller is configured to extract the parameter after the light emitting device turns off;

wherein the output signal is a voltage signal which is a function of the on threshold voltage of the light emitting device.

16. The display according to claim 14, wherein the controller is configured to extract the parameter after the drive transistor turns off;

wherein the output signal is a voltage signal which is a function of the threshold voltage of the drive transistor.

17. The display according to claim 14, wherein the controller is configured to supply a second initial voltage to the second node, and supply the first initial voltage, externally via the first signal line.

18. The display according to claim 14, wherein the controller is configured to supply the first initial voltage to the first node via the first signal line, and to supply a second initial voltage to the second node via a second signal line coupleable to the second node.

19. The display according to claim 14, wherein the controller is configured to supply controlling input signals to the first switching transistor and a second switching transistor coupled between a second signal line and the second node to turn off both the first and second switching transistors to reset the voltages at the first and second nodes.

20. The display according to claim 14, further comprising a third switching transistor controllably coupling a supply voltage to the drive transistor;

wherein the first node is between the third switching transistor and the drive transistor; and

wherein the controller is configured to delay connecting the supply voltage to the drive transistor in step ii) using the third switching transistor.

21. The display according to claim 14, wherein the controller is configured to:

turn on the drive transistor and measure current or voltage of the drive transistor over the first signal line while changing a driving voltage between the gate terminal and the one of the source terminal and the drain terminal of the drive transistor to operate the drive transistor in the linear regime during one time interval and in the saturated regime during a second time interval, and

extract the voltage of the light emitting device from the relationship of the currents or voltages measured with the drive transistor operating in the two regimes.

22. The display according to claim 14, wherein the controller is configured to turn off the drive transistor during step ii);

and

extract an off voltage of the light emitting device when the light emitting device turns off during step iii).

23. The display according to claim 14, wherein the controller is configured to determine a parasitic capacitance by:

determining a first voltage or current on the first node during step i);

determining a second voltage or current on the first node during step iii); and

based on a pixel model, calculate the parasitic capacitance from the first and second voltages or currents.

24. A method of operating a display, the display comprising:

a first signal line for outputting an output signal;

a plurality of pixel circuits, each pixel circuit comprising;

a light emitting device;

a drive transistor for controlling current supplied to the light emitting device, said drive transistor having a gate terminal, a source terminal and a drain terminal;

a storage device coupled between the gate terminal of the drive transistor and one of the source terminal and the drain terminal of the drive transistor, a first node of the pixel circuit located between the storage device and the drive transistor;

a first switching transistor controllably coupling the first signal line to a second node of the pixel circuit located between the storage device and the one of the source terminal and the drain terminal of the drive transistor;

and

a controller coupled to each pixel circuit and capable of supplying controlling input signals to the pixel circuit in a predetermined sequence to produce the output signal which is a function of a parameter of the pixel circuit,

the method comprising;

i) supplying a first initial voltage to the first node;

ii) turning off the first switching transistor, and controlling the drive transistor so that current flows through the light emitting device and the drive transistor, the magnitude of said current being controlled by a gate voltage applied to the gate terminal of the drive transistor discharged by the storage device; and

iii) turning on the first switching transistor and extracting the parameter of the pixel circuit by reading the output signal over the first signal line.

25. The method according to claim 24, wherein step iii) includes extracting the parameter after the light emitting device turns off;

wherein the output signal is a voltage signal which is a function of the threshold voltage of the light emitting device.

26. The method according to claim 24, wherein step iii) includes extracting the parameter after the drive transistor turns off;

wherein the output signal is a voltage signal which is a function of the threshold voltage of the drive transistor.

27. The method according to claim 24, wherein step i) includes supplying a second initial voltage to the second node, and supplying the first initial voltage, externally via the first signal line.

28. The method according to claim 24, wherein step i) includes supplying the first initial voltage to the first node via the first signal line, and supplying a second initial voltage to the second node via a second signal line coupleable to the second node.

29. The method according to claim 24, further comprising supplying controlling input signals to the first switching transistor and a second switching transistor coupled between a second signal line and the second node to turn off both the first and second switching transistors to reset the voltages at the first and second nodes.

30. The method according to claim 24, wherein each pixel further comprises a third switching transistor controllably coupling a supply voltage to the drive transistor;

wherein the first node is between the third switching transistor and the drive transistor; and

wherein the controller is capable of delaying connecting the supply voltage to the drive transistor in step ii) using the third switching transistor.

31. The method according to claim 24, wherein step iii) includes turning on the drive transistor and measuring current or voltage of the drive transistor over the first signal line while changing a driving voltage between the gate terminal and the one of the source terminal and the drain terminal of the drive transistor to operate the drive transistor in the linear regime during one time interval and in the saturated regime during a second time interval, and

extracting the voltage of the light emitting device from the relationship of the currents or voltages measured with the drive transistor operating in the two regimes.

32. The method according to claim 24, further comprising:

turning off the drive transistor during step ii); and

extracting an off voltage of the light emitting device when the light emitting device turns off during step iii).

33. The method according to claim 24, wherein step iii) includes determining a parasitic capacitance by:

determining a first voltage or current on the first node during step i);

determining a second voltage or current on the first node during step iii); and

based on a pixel model, calculate the parasitic capacitance from the first and second voltages or currents.