DISPLAY DEVICE

• US 20190325799A1
• Filed: 04/17/2019
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: TAKEUCHI, YOHEI, WATANABE, TAKUYA, TAGAWA, AKIRA, IWASE, YASUAKI, KUSUMI, TAKATSUGU
• Granted Patent: US 10,777,111 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 3/025 with scanning or deflecting the beams in two directions or dimensions
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A plurality of pixel formation portions in an image display portion are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more. The K pixel formation portions forming each of the pixel groups are connected to the same source bus line. Each of the pixel formation portions is provided with a connection control transistor configured to control an electrical connection state between the corresponding source bus line and a pixel electrode. The K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another. A source driver applies a video signal to each of the source bus lines in a time division manner in each horizontal scanning period.

Claims

1. A display device comprising:

a plurality of video signal lines;

a plurality of scanning signal lines intersecting with the plurality of video signal lines;

an image display portion including a plurality of pixel formation portions each connected to one of the plurality of video signal lines and one of the plurality of scanning signal lines;

a video signal line drive circuit configured to apply video signals to the plurality of video signal lines; and

a scanning signal line drive circuit configured to apply scanning signals to the plurality of scanning signal lines, wherein

the plurality of pixel formation portions are grouped so that K pixel formation portions form each pixel group, where K is an integer of two or more,

the K pixel formation portions forming each of the pixel groups are connected to the same video signal line,

each of the pixel formation portions includes;

a pixel electrode as one of electrodes forming a capacitance; and

a connection control transistor configured to control an electrical connection state between a corresponding video signal line and the pixel electrode,

K connection control transistors included in the K pixel formation portions forming each of the pixel groups become an On state in periods different from one another, and

the video signal line drive circuit applies the video signals to each of the video signal lines in a time division manner in each horizontal scanning period.

2. The display device according to claim 1, wherein

the image display portion further includes a plurality of connection control signal lines configured to transmit connection control signals for controlling an On/Off state of the connection control transistors included in the plurality of pixel formation portions,

each of the pixel formation portions further includes a pixel transistor having a control terminal connected to a corresponding scanning signal line, a first conduction terminal connected to a corresponding connection control signal line, and a second conduction terminal connected to a control terminal of the connection control transistor, and

the connection control transistor has the control terminal connected to the second conduction terminal of the pixel transistor, a first conduction terminal connected to the pixel electrode, and a second conduction terminal connected to the corresponding video signal line.

3. The display device according to claim 2, wherein

the control terminals of K pixel transistors included in the K pixel formation portions forming each of the pixel groups are connected to a same scanning signal line,

as the connection control signal, K connection control signals are prepared, the K connection control signals becoming active at timing different from one another, and

the first conduction terminals of the K pixel transistors included in the K pixel formation portions forming each of the pixel groups are connected to the connection control signal lines configured to transmit the connection control signals different from one another.

4. The display device according to claim 2, wherein

the K is two,

as the connection control signals, a first connection control signal and a second connection control signal that become active at different timing are prepared, and

when two pixel formation portions forming each of the pixel groups are defined as a first pixel formation portion and a second pixel formation portion, with regard to each of the pixel groups,

the control terminal of the pixel transistor included in the first pixel formation portion and the control terminal of the pixel transistor included in the second pixel formation portion are connected to a same scanning signal line,

the first conduction terminal of the pixel transistor included in the first pixel formation portion is connected to a connection control signal line configured to transmit the first connection control signal, and

the first conduction terminal of the pixel transistor included in the second pixel formation portion is connected to a connection control signal line configured to transmit the second connection control signal.

5. The display device according to claim 2, wherein

the control terminals of the K pixel transistors included in the K pixel formation portions forming each of the pixel groups are connected to J scanning signal lines so that (K/J) pixel formation portions correspond to one scanning signal line,

as the connection control signals, (K/J) connection control signals are prepared, the (K/J) connection control signals becoming active at timing different from one another, and

with regard to the K pixel transistors included in the K pixel formation portions forming each of the pixel groups, the first conduction terminals of (K/J) pixel transistors connected to a same scanning signal line are connected to the connection control signal lines configured to transmit the connection control signals different from one another.

6. The display device according to claim 2, wherein

the K is four,

as the connection control signals, a first connection control signal and a second connection control signal that become active at different timing are prepared, and

when the four pixel formation portions forming each of the pixel groups are defined as a first pixel formation portion, a second pixel formation portion, a third pixel formation portion, and a fourth pixel formation portion, with regard to each of the pixel groups,

the control terminal of the pixel transistor included in the first pixel formation portion and the control terminal of the pixel transistor included in the second pixel formation portion are connected to a same scanning signal line,

the control terminal of the pixel transistor included in the third pixel formation portion and the control terminal of the pixel transistor included in the fourth pixel formation portion are connected to a same scanning signal line,

the control terminal of the pixel transistor included in the first pixel formation portion and the control terminal of the pixel transistor included in the third pixel formation portion are connected to different scanning signal lines,

the first conduction terminal of the pixel transistor included in the first pixel formation portion and the first conduction terminal of the pixel transistor included in the third pixel formation portion are connected to a connection control signal line configured to transmit the first connection control signal, and

the first conduction terminal of the pixel transistor included in the second pixel formation portion and the first conduction terminal of the pixel transistor included in the fourth pixel formation portion are connected to a connection control signal line configured to transmit the second connection control signal.