METHOD, SYSTEM AND DEVICE FOR INTEGRATION OF BITCELLS IN A VOLATILE MEMORY ARRAY AND BITCELLS IN A NON-VOLATILE MEMORY ARRAY

• US 20190325919A1
• Filed: 04/23/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Bhargava, Mudit, Das, Shidhartha, Lattimore, George McNeil, Cline, Brian Tracy
• Granted Patent: US 10,607,659 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 2207/2236 Copy
• CPC Class Codes: G11C 2207/2263 Write conditionally, e.g. only if new data and old data differ
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Claims

1. An integrated circuit device, comprising:

at least a first non-volatile memory array to comprise a first plurality of non-volatile memory bitcells;

at least a first volatile memory array to comprise a first plurality of volatile memory bitcells;

a shared decoder circuit to be coupled to the first non-volatile memory array and the first volatile memory array to access one or more of the first plurality of non-volatile memory bitcells and one or more of the first plurality of volatile memory bitcells via assertion of one or more access signals;

a shared bus structure to include at least one non-volatile memory bus to transfer memory states from the first plurality of non-volatile bitcells in read operations and to transfer memory states to the first plurality of non-volatile bitcells in write operations and further to include at least one volatile memory bus to transfer memory states to the first plurality of volatile bitcells in write operations and to transfer memory states from the first plurality of volatile bitcells in read operations; and

at least one external port to transfer signals and/or states representative of input values and/or output values between the shared bus structure and one or more external terminals of the integrated circuit device,

wherein the shared bus structure to be coupled to the at least one non-volatile memory bus and the at least one volatile memory bus to enable transfer of signals and/or states between the at least one external port and the at least one non-volatile memory bus or the at least one volatile memory bus, or a combination thereof, and/or to enable a transfer of signals and/or states between the at least one non-volatile memory bus and the at least one volatile memory bus.

2. The integrated circuit device of claim 1, wherein the plurality of non-volatile memory bitcells to comprise correlated electron switch (CES) elements adaptable to be placed in first impedance state to comprise a conductive and/or low impedance state and wherein the second impedance state to comprise an insulative and/or high impedance state.

3. The integrated circuit device of claim 1, and further comprising:

wherein the shared decoder circuit to apply the one or more access signals to at least one of a plurality of wordlines to access the one or more of the first plurality of volatile memory bitcells and the one or more of the first plurality of non-volatile memory bitcells.

4. The integrated circuit device of claim 3, wherein the shared decoder circuit further to apply the one or more access signals to the plurality of wordlines to access the one or more of the first plurality of volatile memory bitcells and the one or more of the first plurality of non-volatile memory bitcells.

5. The integrated circuit device of claim 1, wherein the shared decoder circuit to assert the one or more access signals to a first wordline, wherein a first portion of the first wordline to access at least one of the first plurality of volatile memory bitcells and wherein a second portion of the first wordline to access at least one of the first plurality of non-volatile memory bitcells.

6. The integrated circuit device of claim 3, wherein one or more first wordlines of the plurality of wordlines to maintain a first access signal at a first voltage to access the one or more of the first plurality of volatile memory bitcells, and wherein one or more second wordlines of the plurality of wordlines to maintain a second access signal at a second voltage different from the first voltage to access the one or more of the first plurality of non-volatile memory bitcells.

7. The integrated circuit device of claim 3, wherein the shared decoder circuit further to:

apply a first access signal of the one or more access signals to a selected wordline for a read operation to detect one or more states of the one or more of the first plurality of volatile memory bitcells; and

apply a second access signal of the one or more access signals to the selected wordline for a write operation to write to the one or more of the first plurality of non-volatile memory bitcells based, at least in part, on at least one of the one or more detected states.

8. The integrated circuit device of claim 7, wherein the shared decoder circuit further to:

apply the first access signal to the selected wordline for a read operation to detect one or more memory states of the one or more of the first plurality of non-volatile memory bitcells; and

apply a second access signal to the selected wordline for a write operation to write to the one or more of the first plurality of volatile memory bitcells based on at least one of the one or more detected memory states.

9. The integrated circuit device of claim 3, wherein the shared decoder circuit further to:

apply a first access signal of the one or more access signals to a selected wordline of the plurality of wordlines to access the one or more of the first plurality of volatile memory bitcells and the one or more of the first plurality of non-volatile memory bitcells; and

while the first access signal is maintained at a particular voltage to access the one or more of the first plurality of volatile memory bitcells and the one or more of the first plurality of non-volatile memory bitcells, execute a read operation to detect one or more memory states of at least one of the one or more of the plurality of volatile memory bitcells and execute a write operation to at least one of the one or more of the first plurality of non-volatile memory bitcells based, at least in part, on at least one of the one or more detected memory states.

10. The integrated circuit device of claim 9, and further comprising:

at least one sense amplifier to detect the one or more memory states of the at least one of the one or more of the first plurality of volatile memory bitcells;

at least one write driver circuit to generate a programming signal to place the at least one of the one or more of the first plurality of non-volatile memory bitcells in the one or more detected memory states; and

a bus circuit to transmit signals and/or states representative of the one or more detected memory states between the at least one sense amplifier and the at least one write driver circuit.

11. The integrated circuit device of claim 3, wherein the shared decoder circuit further configured to apply the one or more access signals to a plurality of wordlines, wherein at least one of the plurality of wordlines to be connected to the one or more of the first plurality of volatile memory bitcells and the one or more of the first plurality of non-volatile memory bitcells.

12. The integrated circuit device of claim 1, and further comprising at least a second volatile memory array to comprise a second plurality of volatile memory bitcells;

and

the shared decoder circuit to assert a first access signal on at least a first wordline coupled to at least a portion of the first plurality of non-volatile memory bitcells, a portion of the first plurality of volatile memory bitcells and a portion of the second plurality of volatile memory bitcells, and wherein the portion of the first plurality of non-volatile memory bitcells to be coupled to the first wordline between the portion of the first plurality of volatile memory bitcells and the portion of the second plurality of volatile memory bitcells.

13. The integrated circuit device of claim 12, and further comprising:

a first access device to be coupled to the first wordline between the first plurality of volatile memory bitcells and the portion of first plurality of non-volatile memory bitcells to disconnect the first plurality of volatile memory bitcells while accessing the second plurality of volatile memory bitcells; and

a second access device to be coupled by the first wordline between the second plurality of volatile memory bitcells and the portion of the first plurality of non-volatile memory bitcells to disconnect the second plurality of volatile memory bitcells while accessing the first plurality of volatile memory bitcells.

14. The integrated circuit device of claim 1, wherein:

the first volatile memory array to comprise at least a first column of volatile memory bitcells, wherein volatile memory bitcells in the first column of volatile memory bitcells to be accessible via one or more common first bitlines;

the first non-volatile memory array to comprise at least a second column of non-volatile memory bitcells, wherein non-volatile memory bitcells in the second column of non-volatile memory bitcells to be accessible via one or more common second bitlines; and

a circuit to transfer signals and/or states representative of one or more values between one or more selected volatile memory bitcells in the first column of volatile memory bitcells and one or more selected non-volatile memory bitcells in the second column of non-volatile memory bitcells, the first column of volatile memory bitcells and the second column of non-volatile memory bitcells to be adjacent.

15. The integrated circuit device of claim 14, wherein the one or more selected volatile memory bitcells and the one or more selected non-volatile memory bitcells to be selectable responsive to a wordline signal.

16. The integrated circuit device of claim 14, wherein the circuit to transfer the signals and/or states representative of the one or more values between the one or more selected volatile memory bitcells and the one or more selected non-volatile memory bitcells further to comprise a read circuit to be connected to the one or more common first bitlines to detect a signal and/or state representative of a value to be stored in at least one of the one or more selected volatile memory bitcells and a write driver circuit to be connected to the one or more common second bitlines to generate a programming signal to store the detected signal and/or state representative of the value stored in the at least one of the one or more selected volatile memory bitcells in at least one of the one or more selected non-volatile memory bitcells, and

wherein the circuit to transfer the signals and/or states representative of the one or more values between the one or more selected volatile memory bitcells and the one or more selected non-volatile memory bitcells further to comprise a read circuit to be connected to the one or more common second bitlines to detect a signal and/or state representative of a value to be stored in at least one of the one or more selected non-volatile memory bitcells and a write driver circuit to be connected to the one or more common first bitlines to generate a programming signal to store the detected signal and/or state representative of the value stored in the at least one of the one or more selected non-volatile memory bitcells in at least one of the one or more selected volatile memory bitcells.

17. A method comprising:

applying, via a shared decoder circuit, a first access signal to at least a first wordline of a plurality of wordlines to access one or more volatile memory bitcells in a first volatile memory array formed in an integrated circuit device and one or more non-volatile memory bitcells in a non-volatile memory array formed in the integrated circuit device;

applying one or more first signals to one or more external terminals of the integrated circuit device to access at least some volatile memory bitcells in the first volatile memory array; and

applying one or more second signals to the one or more external terminals of the integrated circuit device to access at least some of the one or more non-volatile memory bitcells in the non-volatile memory array,

wherein the one or more external terminals are coupled to a port of the integrated circuit device for accessing the first volatile memory array or the non-volatile memory array, or a combination thereof.

18. The method of claim 17, wherein the applying the first access signal to the first wordline to access the one or more volatile memory bitcells and the one or more non-volatile memory bitcells in the non-volatile memory array further comprises applying the first access signal to at least a first portion of the first wordline to access the one or more volatile memory bitcells and applying the first access signal to at least a second portion of the first wordline to access the one or more non-volatile memory bitcells in the non-volatile memory array.

19. The method of claim 17, and further comprising transferring one or more stored signals and/or states representative of one or more values between the one or more volatile memory bitcells and the one or more non-volatile memory bitcells while one or more volatile memory bitcells and one or more non-volatile memory bitcells are accessed responsive to the applying the first access signal to the at least the first wordline of the plurality of wordlines.

20. The method of claim 17, wherein the one or more non-volatile memory bitcells in the non-volatile memory array are coupled to one or more volatile memory bitcells in a second volatile memory array formed in the integrated circuit device, the method further comprising:

disconnecting the one or more volatile memory bitcells in the second volatile memory array from the one or more non-volatile memory bitcells in the non-volatile memory array while applying the first access signal to the at least the first wordline of the plurality of wordlines to access the one or more volatile memory bitcells in the first volatile memory array and the one or more non-volatile memory bitcells in the non-volatile memory array.

21. A method comprising:

applying one or more first signals to one or more external terminals of an integrated circuit device to access one or more volatile memory bitcells in a volatile memory array formed in an integrated circuit device; and

applying one or more second signals to the one or more external terminals of the integrated circuit device to access one or more non-volatile memory bitcells in a non-volatile memory array formed in the integrated circuit device,

wherein at least one of the one or more volatile memory bitcells and at least one of the one or more non-volatile memory bitcells are connected to a wordline of a plurality of wordlines formed in the integrated circuit device,

wherein a shared decoder circuit coupled to the first non-volatile memory array and the first volatile memory array to access the one or more non-volatile memory bitcells and the one or more volatile memory bitcells by applying an access signal to the wordline of the plurality of wordlines, and

wherein the one or more external terminals are coupled to a port of the integrated circuit device, the port for accessing the volatile memory array or the non-volatile memory array, or a combination thereof.

22. The method of claim 21, and further comprising:

transferring one or more signals and/or states representative of a value between a selected volatile memory bitcell in a first selected column of a first plurality of columns of the volatile memory array and a selected non-volatile memory bitcell in a second selected column of a second plurality of columns of the non-volatile memory array, the first selected one of the first plurality of columns of the volatile memory array and the selected one of the second plurality of columns of the non-volatile memory array being adjacent, wherein;

one or more volatile memory bitcells of the first column of the volatile memory array are accessible via one or more common first bitlines;

one or more non-volatile memory bitcells of the second column of the non-volatile memory array are accessible via one or more common second bitlines; and

the first and second columns are configured in an array such that the first plurality of columns of the volatile memory array alternate and interleave with the second plurality columns of the non-volatile memory array.

23. The method of claim 21, and further comprising transferring one or more signals and/or states representative of one or more values between the volatile memory array and the non-volatile memory array using a shared bus structure.

24. The method of claim 23, and further comprising transferring one or more signals and/or states between the shared bus structure and the one or more external terminals,

wherein the shared decoder circuit further to assert one or more second access signals on a plurality of wordlines, wherein at least one of the plurality of wordlines is connected to at least one of the volatile memory bitcells and at least one of the non-volatile memory bitcells.