SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
First Claim
1. A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:
- receiving a request for performing a target operation from a controller configured to control the semiconductor memory device;
generating a synchronizing signal for performing the target operation; and
detecting temperatures of memory cells included in the semiconductor memory device in response to the synchronizing signal,wherein the target operation includes at least one of a program related operation, a read related operation, and an erase related operation for the plurality of memory cells.
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Accused Products
Abstract
There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.
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18 Claims
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1. A method of operating a semiconductor memory device including a plurality of memory cells, the method comprising:
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receiving a request for performing a target operation from a controller configured to control the semiconductor memory device; generating a synchronizing signal for performing the target operation; and detecting temperatures of memory cells included in the semiconductor memory device in response to the synchronizing signal, wherein the target operation includes at least one of a program related operation, a read related operation, and an erase related operation for the plurality of memory cells. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory device comprising:
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a memory cell array including a plurality of memory cells; an operation control signal generator configured to receive a request for performing a target operation from a controller and to generate a synchronizing signal for performing the target operation; and a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal, wherein the target operation includes at least one of a program related operation, a read related operation, and an erase related operation for the plurality of memory cells. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification