SEMICONDUCTOR DEVICE

• US 20190325925A1
• Filed: 11/21/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Hong Gyeom, RA, Dae Ho, YOON, Byung Kuk, HAN, Min Sik
• Granted Patent: US 10,762,933 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Claims

1. A semiconductor device comprising:

a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal;

a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal; and

a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

2. The semiconductor device according to claim 1, wherein the latency signal is enabled for a predetermined time period during a read operation, and wherein the order control signal has a logic level for determining a data alignment order.

3. The semiconductor device according to claim 1,

wherein the latch output signal comprises first, second, third, and fourth latch output signals, and

wherein the latch control circuit comprises:

a latch input signal generation circuit configured to generate the latch input signal, which is enabled in synchronization with an internal clock in response to the latency signal; and

a latch output signal generation circuit configured to generate the first, second, third, and fourth latch output signals, which are sequentially enabled in synchronization with the internal clock in response to the order control signal.

4. The semiconductor device according to claim 3, wherein the latch input signal generation circuit comprises:

a latch signal generation circuit configured to latch the latency signal in synchronization with the internal clock and configured to output the latched latency signal as a latch signal; and

a logic circuit configured to generate the latch input signal from the latch signal in response to the internal clock.

5. The semiconductor device according to claim 3, wherein the latch output signal generation circuit comprises:

a transfer control signal generation circuit configured to generate a transfer control signal, which is enabled in response to the internal clock and the latency signal;

a first signal transfer circuit configured to be initialized to a voltage level of a ground voltage in synchronization with the internal clock and configured to generate the first latch output signal and the second latch output signal, which are sequentially enabled in synchronization with the internal clock depending on a logic level of the order control signal when the transfer control signal is enabled; and

a second signal transfer circuit configured to be initialized to the voltage level of the ground voltage in synchronization with the internal clock and configured to generate the third latch output signal and the fourth latch output signal, which are sequentially enabled in synchronization with the internal clock depending on the logic level of the order control signal when the transfer control signal is enabled.

6. The semiconductor device according to claim 5,

wherein the first signal transfer circuit generates the first latch output signal and the second latch output signal, which are enabled when the order control signal has a first logic level, and

wherein the second signal transfer circuit generates the third latch output signal and the fourth latch output signal, which are enabled when the order control signal has a second logic level.

7. The semiconductor device according to claim 1,

wherein the latch data comprises first, second, third, and fourth latch data, and wherein the output data comprises first, second, third, and fourth output data and wherein the latch output signal comprises first, second, third, and fourth latch output signals, and

wherein the data output circuit comprises:

a first data output circuit configured to latch the first latch data in response to the latch input signal, and configured to output the latched first latch data as the first output data in response to the first latch output signal;

a second data output circuit configured to latch the second latch data in response to the latch input signal, configured to and output the latched second latch data as the second output data in response to the second latch output signal;

a third data output circuit configured to latch the third latch data in response to the latch input signal, and configured to output the latched third latch data as the third output data in response to the third latch output signal; and

a fourth data output circuit configured to latch the fourth latch data in response to the latch input signal, and configured to output the latched fourth latch data as the fourth output data in response to the fourth latch output signal.

8. The semiconductor device according to claim 7, wherein the first data output circuit comprises:

a first latch circuit configured to latch the first latch data in response to the latch input signal, and configured to output the latched first latch data as first internal latch data; and

a second latch circuit configured to latch the first internal latch data in response to the first latch output signal, and configured to output the latched first internal latch data as the first output data.

9. The semiconductor device according to claim 7, wherein the second data output circuit comprises:

a third latch circuit configured to latch the second latch data in response to the latch input signal, and configured to output the latched second latch data as second internal latch data; and

a fourth latch circuit configured to latch the second internal latch data in response to the second latch output signal, and configured to output the latched second internal latch data as the second output data.

10. The semiconductor device according to claim 7, wherein the third data output circuit comprises:

a fifth latch circuit configured to latch the third latch data in response to the latch input signal, and configured to output the latched third latch data as third internal latch data; and

a sixth latch circuit configured to latch the third internal latch data in response to the third latch output signal, and configured to output the latched third internal latch data as the third output data.

11. The semiconductor device according to claim 7, wherein the fourth data output circuit comprises:

a seventh latch circuit configured to latch the fourth latch data in response to the latch input signal, and configured to output the latched fourth latch data as fourth internal latch data; and

an eighth latch circuit configured to latch the fourth internal latch data in response to the fourth latch output signal, and configured to output the latched fourth internal latch data as the fourth output data.

12. A semiconductor device comprising:

a pipe control circuit configured to generate first, second, third, and fourth pipe input signals, which are sequentially enabled in response to a read signal, and configured to generate first, second, third, and fourth pipe output signals, which are sequentially enabled in synchronization with an internal clock in response to a latency signal;

a pipe latch circuit configured to latch first, second, third, and fourth input data in response to the first, second, third, and fourth pipe input signals, and configured to output the latched first, second, third, and fourth input data as first, second, third, and fourth latch data in response to the first, second, third, and fourth pipe output signals; and

a data output circuit configured to latch the first, second, third, and fourth latch data in response to a latch input signal, and configured to output the latched first, second, third, and fourth latch data as first, second, third, and fourth output data in response to first, second, third, and fourth latch output signals.

13. The semiconductor device according to claim 12, wherein the latency signal is enabled for a predetermined time period during a read operation.

14. The semiconductor device according to claim 12, wherein the data output circuit outputs the first, second, third, and fourth output data by performing an alignment operation for the first, second, third, and fourth latch data in response to the first, second, third, and fourth latch output signals.

15. The semiconductor device according to claim 12, wherein the pipe control circuit comprises:

a pipe input signal generation circuit configured to generate the first, second, third, and fourth pipe input signals, which are sequentially enabled in response to the read signal; and

a pipe output signal generation circuit configured to generate the first, second, third, and fourth pipe output signals, which are sequentially enabled in synchronization with the internal clock in response to the latency signal.

16. The semiconductor device according to claim 15, wherein the pipe input signal generation circuit comprises:

a pulse signal generation circuit configured to generate a pulse signal, which comprises a pulse generated in response to the read signal;

a transfer signal generation circuit configured to generate first, second, third, and fourth transfer signals, which are sequentially enabled in response to the pulse signal; and

a logic circuit configured to output the first, second, third, and fourth pipe input signals by inverting and buffering the first, second, third, and fourth transfer signals in response to the pulse signal.

17. The semiconductor device according to claim 16, wherein the first, second, third, and fourth transfer signals are initialized to have a first set combination, and wherein the first set combination corresponds to the first, second, and third transfer signals having first logic levels and the fourth transfer signal having a second logic level.

18. The semiconductor device according to claim 15, wherein the pipe output signal generation circuit comprises:

a control signal generation circuit configured to latch the latency signal in synchronization with the internal clock, and configured to output the latched latency signal as a control signal; and

a signal transfer circuit configured to generate the first, second, third, and fourth pipe output signals, which are sequentially enabled in response to the control signal.

19. The semiconductor device according to claim 18, wherein the first, second, third, and fourth pipe output signals are initialized to have a second set combination, and wherein the second set combination corresponds to the first pipe output signal having a second logic level and the second, third, and fourth pipe output signals having first logic levels.

20. The semiconductor device according to claim 12, wherein the data output circuit comprises:

a first data output circuit configured to latch the first latch data in response to the latch input signal, and configured to output the latched first latch data as the first output data in response to the first latch output signal;

a second data output circuit configured to latch the second latch data in response to the latch input signal, and configured to output the latched second latch data as the second output data in response to the second latch output signal;

a third data output circuit configured to latch the third latch data in response to the latch input signal, and configured to output the latched third latch data as the third output data in response to the third latch output signal; and

a fourth data output circuit configured to latch the fourth latch data in response to the latch input signal, and configured to output the latched fourth latch data as the fourth output data in response to the fourth latch output signal.

21. The semiconductor device according to claim 12, further comprising:

a latch control circuit configured to generate the latch input signal, which is enabled in response to the latency signal and the first, second, third, and fourth latch output signals, which are enabled in response to an order control signal.

22. The semiconductor device according to claim 21, wherein the latch control circuit comprises:

a latch input signal generation circuit configured to generate the latch input signal, which is enabled in synchronization with the internal clock in response to the latency signal; and

a latch output signal generation circuit configured to generate the first, second, third, and fourth latch output signals, which are sequentially enabled in synchronization with the internal clock in response to the order control signal.

23. The semiconductor device according to claim 22, wherein the latch input signal generation circuit comprises:

a latch signal generation circuit configured to latch the latency signal in synchronization with the internal clock, and configured to output the latched latency signal as a latch signal; and

a logic circuit configured to generate the latch input signal from the latch signal in response to the internal clock.

24. The semiconductor device according to claim 22, wherein the latch output signal generation circuit comprises:

a transfer control signal generation circuit configured to generate a transfer control signal, which is enabled in response to the internal clock and the latency signal;

a first signal transfer circuit configured to be initialized to a voltage level of a ground voltage in synchronization with the internal clock and configured to generate the first latch output signal and the second latch output signal, which are sequentially enabled in synchronization with the internal clock depending on a logic level of the order control signal when the transfer control signal is enabled; and

a second signal transfer circuit configured to be initialized to the voltage level of the ground voltage in synchronization with the internal clock and configured to generate the third latch output signal and the fourth latch output signal which are sequentially enabled in synchronization with the internal clock depending on the logic level of the order control signal when the transfer control signal is enabled.

25. The semiconductor device according to claim 24,

wherein the first signal transfer circuit generates the first latch output signal and the second latch output signal, which are enabled when the order control signal has a first logic level, and

wherein the second signal transfer circuit generates the third latch output signal and the fourth latch output signal, which are enabled when the order control signal has a second logic level.