RESISTIVE MEMORY DEVICE HAVING MEMORY CELL ARRAY AND SYSTEM INCLUDING THE SAME

• US 20190325933A1
• Filed: 11/19/2018
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Postech Academy-Industry Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Jaeho, Sim, Jaeyoon, Lee, Kyeongjun
• Granted Patent: US 10,546,623 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.

Claims

1. A resistive memory device comprising:

a memory cell array in which a plurality of memory cells are arranged in a matrix,

wherein each of the plurality of memory cells comprises;

a variable resistor comprising a first end connected to a bit line, and a second end;

a row transistor connected between a row source line and the second end of the variable resistor, wherein the row transistor is selectable by a row word line; and

a column transistor connected between a column source line and the second end of the variable resistor, wherein the column transistor is selectable by a column word line,

wherein, based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and

wherein, based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.

2. The resistive memory device of claim 1, further comprising a row sense amplifier connected to the row source line,

wherein, based on the row transistor being selected by the row word line, a logic value that is stored in the variable resistor is identified using the row sense amplifier.

3. The resistive memory device of claim 1, wherein the second data is read in the row direction of any one or any combination of first memory cells that are arranged along the row word line and connected to the row word line, among the plurality of memory cells.

4. The resistive memory device of claim 1, further comprising a column sense amplifier connected to the column source line,

wherein, based on the column transistor being selected by the column word line, a logic value that is stored in the variable resistor is identified using the column sense amplifier.

5. The resistive memory device of claim 1, wherein the second data is read in the column direction of any one or any combination of second memory cells that are arranged along the column word line and connected to the column word line, among the plurality of memory cells.

6. The resistive memory device of claim 1, further comprising a write driver connected between the row source line and the bit line,

wherein, based on the row transistor being selected by the row word line, a logic value that is stored in the variable resistor is changed or maintained, based on a voltage applied to the row source line and the bit line by the write driver.

7. The resistive memory device of claim 1, wherein, based on the column transistor being selected by the column word line, a logic value that is stored in the variable resistor is changed or maintained, based on a voltage applied to the column source line and the bit line.

8. The resistive memory device of claim 1, wherein a first gate of the column transistor has a first width greater than a second width of a second gate of the row transistor, and

a negative voltage is applied to either one or both of the first end and the second end of the variable resistor.

9. The resistive memory device of claim 1, wherein the resistive memory device is any one or any combination of ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), nano-floating gate memory (NFGM), phase-change random access memory (PRAM), resistive random access memory (RRAM), static random access memory (SRAM), and flash memory.

10. The resistive memory device of claim 1, wherein the variable resistor stores at least one logic value, wherein each of the at least one logic value corresponds to a bit.

11. A system comprising:

a resistive memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix;

a memory controller configured to control the resistive memory device;

an input/output device configured to receive first data to be written to the resistive memory device, and output second data that is read from the resistive memory device; and

a processor configured to control the memory controller and the input/output device,

wherein each of the plurality of memory cells comprises;

a variable resistor comprising a first end connected to a bit line, and a second end;

a row transistor connected between a row source line and the second end of the variable resistor, wherein the row transistor is selectable by a row word line; and

a column transistor connected between a column source line and the second end of the variable resistor, wherein the column transistor is selectable by a column word line,

wherein, based on the row transistor being selected, the first data is written or the second is read in a row direction of the memory cell array, and

wherein, based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.

12. The system of claim 11, wherein the resistive memory device further comprises a row sense amplifier connected to the row source line,

wherein, based on the row transistor being selected by the row word line, a logic value that is stored in the variable resistor is identified using the row sense amplifier.

13. The system of claim 11, wherein the second data is read in the row direction of any one or any combination of first memory cells that are arranged along the row word line and connected to the row word line, among the plurality of memory cells.

14. The system of claim 11, wherein the resistive memory device further comprises a column sense amplifier connected to the column source line, wherein, based on the column transistor being selected by the column word line, a logic value that is stored in the variable resistor is identified using the column sense amplifier.

15. The system of claim 11, wherein the second data is read in the column direction of any one or any combination of second memory cells that are arranged along the column word line and connected to the column word line, among the plurality of memory cells.

16. The system of claim 11, wherein the resistive memory device further comprises a write driver connected between the row source line and the bit line,

wherein, based on the row transistor being selected by the row word line a logic value that is stored in the variable resistor is changed or maintained, based on a voltage applied to the row source line and the bit line by the write driver.

17. The system of claim 11, wherein, based on the column transistor being selected by the column word line, a logic value that is stored in the variable resistor is changed or maintained, based on a voltage applied to the column source line and the bit line.

18. The system of claim 11, wherein a first gate of the column transistor has a first width greater than a second width of a second gate of the row transistor, and

a negative voltage is applied to either one or both of the first end and the second end of the variable resistor.

19. The system of claim 11, wherein the resistive memory device is any one or any combination of ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), nano-floating gate memory (NFGM), phase-change random access memory (PRAM), resistive random access memory (RRAM), static random access memory (SRAM), and flash memory.

20. The system of claim 11, wherein the variable resistor stores at least one logic value, wherein each of the at least one logic value corresponds to a bit.