MULTI-PHASE CLOCK DIVISION

• US 20190325937A1
• Filed: 06/28/2019
• Published: 10/24/2019
• Est. Priority Date: 12/18/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Penney, Daniel B.
• Granted Patent: US 10,885,968 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

Claims

1. A semiconductor device comprising:

memory;

a command interface configured to receive a write command to write data to the memory;

a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and

phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory.

2. The semiconductor device of claim 1, wherein the plurality of phases comprises four phases.

3. The semiconductor device of claim 2, wherein:

a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe;

a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe;

a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses; and

a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe.

4. The semiconductor device of claim 1, comprising a toggle flip-flop that is configured to:

receive the data strobe; and

toggle between a first mode and a second mode with each pulse of the data strobe, wherein the first mode directs an output of the toggle flip-flop to a first channel, and the second mode directs the output to a second channel.

5. The semiconductor device of claim 4, wherein the first channel comprises:

a first rising edge flip-flop that receives the output and uses the data strobe to output every other rising edge of the data strobe; and

a second rising edge flip-flop that receives the output and uses the data strobe to output alternative rising edges between the every other rising edge of the data strobe.

6. The semiconductor device of claim 5, wherein the second channel comprises:

a first falling edge flip-flop that receives the output and uses the data strobe to output every other falling edge of the data strobe; and

a second falling edge flip-flop that receives the output and uses the data strobe to output alternative falling edges between the every other falling edges of the data strobe.

7. The semiconductor device of claim 6, wherein using the data strobe to output every other falling edge and alternative falling edges comprises using a data strobe false that is an inversion of the data strobe.

8. The semiconductor device of claim 6, wherein the second channel comprises a latch to track falling edges of the data strobe.

9. The semiconductor device of claim 1, comprising an amplifier that changes power of the data strobe from an external level to an internal level.

10. A semiconductor device comprising:

memory;

a command interface configured to receive a write command to write data to the memory;

a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and

phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein pairs of phases of the plurality of phases correspond to corresponding rising and falling edges of the data strobe.

11. The semiconductor device of claim 10, wherein

a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe;

a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe;

a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses; and

a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe.

12. The semiconductor device of claim 10, wherein the phase division circuitry comprises count detection circuitry configured to count bits received for a phase of the plurality of phases.

13. The semiconductor device of claim 10, comprising a toggle flip-flop that is configured to:

receive the data strobe; and

toggle between a first mode and a second mode with each pulse of the data strobe, wherein the first mode directs an output of the toggle flip-flop to a first channel, and the second mode directs the output to a second channel.

14. The semiconductor device of claim 10, comprising multiplexor that selects between a delay-bypassed route and a delayed bit counting route using the signal.

15. A semiconductor device comprising:

memory banks;

a command interface configured to receive a write command to write data to the memory banks;

a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and

phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises count detection circuitry configured to count bits received for a phase of the plurality of phases.

16. The memory device of claim 15, wherein the phase division circuitry comprises a channel for each phase of the plurality of phases, and the phase detection circuitry is configured to determine whether a first channel or a second channel have begun counting bits first.

17. The memory device of claim 16, wherein the first channel and the second channel correspond to phases of the plurality of phases having an edge-type, and the edge-type comprises rising edges or falling edges of the data strobe.

18. The memory device of claim 16, comprising selection circuitry configured to output a signal based at least in part on whether the second channel is currently capturing a write command when the selection circuitry is in the first channel.

19. The memory device of claim 15, comprising:

delay circuitry; and

selection circuitry configured to output a signal indicating whether to use the delay circuitry based at least in part on whether a write preamble for the write command is longer than a threshold value.

20. The memory device of claim 19, wherein the selector comprises a multiplexor that uses the signal to select whether to use the delay circuitry.