MULTI-PHASE CLOCK DIVISION
1. A semiconductor device comprising:
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory.
Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
- 1. A semiconductor device comprising:
memory; a command interface configured to receive a write command to write data to the memory; a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- 10. A semiconductor device comprising:
memory; a command interface configured to receive a write command to write data to the memory; phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein pairs of phases of the plurality of phases correspond to corresponding rising and falling edges of the data strobe.
- View Dependent Claims (11, 12, 13, 14)
- 15. A semiconductor device comprising:
memory banks; a command interface configured to receive a write command to write data to the memory banks; phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises count detection circuitry configured to count bits received for a phase of the plurality of phases.
- View Dependent Claims (16, 17, 18, 19, 20)
This application is a continuation of U.S. application Ser. No. 16/200,460, filed Nov. 26, 2018, which is a continuation of U.S. application Ser. No. 15/845,874, filed Dec. 18, 2017, now U.S. Pat. No. 10,339,997, which issued on Jun. 20, 2019, both of which are entitled “MULTI-PHASE CLOCK DIVISION,” the contents of which are herein expressly incorporated by reference for all purposes.
Embodiments of the present disclosure relate generally to the field of semiconductor devices. More specifically, embodiments of the present disclosure relate to using a multi-phase clock when the starting phase is unknown.
Semiconductor devices (e.g., memory devices) often utilize clocks to perform functions. As frequency speeds increase, it may be helpful to divide a fast clock into multiple phases for internal use of a portion (e.g., dynamic random-access memory (DRAM). However, by dividing the clock into multiple phases, it may be unknown which starting phase first receives a first incoming clock for the clock. Variable write preamble lengths may also cause incorrect bit counting in a phase of the multiple phases when write preamble lengths change from a default length.
Embodiments of the present disclosure may be directed to one or more of the problems set forth above.
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers'"'"' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
At fast clock frequencies, such as those used for DDR5, an external clock frequency may be divided for internal use by the DRAM. For example, a number (e.g., 4) phases may be generated internally for the single external clock. When dividing the clock for a data strobe pin (DQS), the starting state of the multi-phase generator may not be known at the time a write command is entered because the DQS clock may start and stop only when entering write data bursts. These bursts may come so close together that there is not enough time to reset the DQS clock circuitry between bursts. However, which phase coming out of the generator is leading should be known in order to correctly capture and order the write data.
Furthermore, if a length of a write preamble is programmable, a period at which to begin counting bits in the DQS phases may cause incorrect bit counting without optional delays that are used to delay counting bits until an appropriate period of time has elapsed. Accordingly, delay circuitry may be included that is selected for use when a first preamble length (e.g., 2 or 3 cycles) is used and may be bypassed when a second preamble length (e.g., 1 cycle) is used.
Turning now to the figures,
The memory device 10, may include a number of memory banks 12. The memory banks 12 may be DDR5 SDRAM memory banks, for instance. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) that are arranged on dual inline memory modules (DIMMS). Each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a number of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For instance, for an 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged into 8 bank groups, each bank group including 2 memory banks. For a 16 Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged into 8 bank groups, each bank group including 4 memory banks, for instance. Various other configurations, organization and sizes of the memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.
The memory device 10 may include a command interface 14 and an input/output (110) interface 16. The command interface 14 is configured to provide a number of signals (e.g., signals 15) from an external device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transmission and receipt of data to be written to or read from the memory device 10.
As will be appreciated, the command interface 14 may include a number of circuits, such as a clock input circuit 18 and a command address input circuit 20, for instance, to ensure proper handling of the signals 15. The command interface 14 may receive one or more clock signals from an external device. Generally, double data rate (DDR) memory utilizes a differential pair of system clock signals, referred to herein as the true clock signal (Clk_t/) and the bar clock signal (Clk_b). The positive clock edge for DDR refers to the point where the rising true clock signal Clk_t/crosses the falling bar clock signal Clk_b, while the negative clock edge indicates that transition of the falling true clock signal Clk_t and the rising of the bar clock signal Clk_b. Commands (e.g., read command, write command, etc.) are typically entered on the positive edges of the clock signal and data is transmitted or received on both the positive and negative clock edges.
The clock input circuit 18 receives the true clock signal (Clk_t/) and the bar clock signal (Clk_b) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase controlled internal clock signal LCLK is supplied to the I/O interface 16, for instance, and is used as a timing signal for determining an output timing of read data. In some embodiments, as discussed below, the clock input circuit 18 may include circuitry that splits the clock signal into multiple (e.g., 4) phases. The clock input circuit 18 may also include phase detection circuitry to detect which phase receives a first pulse when sets of pulses occur too frequently to enable the clock input circuit 18 to reset between sets of pulses.
The internal clock signal(s)/phases CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For instance, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from the command bus 34 and may decode the command signals to provide various internal commands. For instance, the command decoder 32 may provide command signals to the DLL circuit 30 over the bus 36 to coordinate generation of the phase controlled internal clock signal LCLK. The phase controlled internal clock signal LCLK may be used to clock data through the IO interface 16, for instance.
Further, the command decoder 32 may decode commands, such as read commands, write commands, mode-register set commands, activate commands, etc., and provide access to a particular memory bank 12 corresponding to the command, via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks 12.
The memory device 10 executes operations, such as read commands and write commands, based on the command/address signals received from an external device, such as a processor. In one embodiment, the command/address bus may be a 14-bit bus to accommodate the command/address signals (CA<13:0>). The command/address signals are clocked to the command interface 14 using the clock signals (Clk_t/and Clk_b). The command interface may include a command address input circuit 20 which is configured to receive and transmit the commands to provide access to the memory banks 12, through the command decoder 32, for instance. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables the memory device 10 to process commands on the incoming CA<13:0> bus. Access to specific banks 12 within the memory device 10 is encoded on the CA<13:0> bus with the commands.
In addition, the command interface 14 may be configured to receive a number of other command signals. For instance, a command/address on die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) may be used to reset the command interface 14, status registers, state machines and the like, during power-up for instance. The command interface 14 may also receive a command/address invert (CAI) signal which may be provided to invert the state of command/address signals CA<13:0> on the command/address bus, for instance, depending on the command/address routing for the particular memory device 10. A mirror (MIR) signal may also be provided to facilitate a mirror function. The MIR signal may be used to multiplex signals so that they can be swapped for enabling certain routing of signals to the memory device 10, based on the configuration of multiple memory devices in a particular application. Various signals to facilitate testing of the memory device 10, such as the test enable (TEN) signal, may be provided, as well. For instance, the TEN signal may be used to place the memory device 10 into a test mode for connectivity testing.
The command interface 14 may also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain errors that may be detected. For instance, an alert signal (ALERT_n) may be transmitted from the memory device 10 if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. Further, the bus and pin for transmitting the alert signal (ALERT_n) from the memory device 10 may be used as an input pin during certain operations, such as the connectivity test mode executed using the TEN signal, as described above.
Data may be sent to and from the memory device 10, utilizing the command and clocking signals discussed above, by transmitting and receiving data signals 44 through the TO interface 16. More specifically, the data may be sent to or retrieved from the memory banks 12 over the datapath 46, which includes a plurality of bi-directional data buses. Data IO signals, generally referred to as DQ signals, are generally transmitted and received in one or more bi-directional data busses. For certain memory devices, such as a DDR5 SDRAM memory device, the IO signals may be divided into upper and lower bytes. For instance, for a x16 memory device, the IO signals may be divided into upper and lower IO signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to upper and lower bytes of the data signals, for instance.
To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices may utilize data strobe signals, generally referred to as DQS signals. The DQS signals are driven by the external processor or controller sending the data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For read commands, the DQS signals are effectively additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. As with the clock signals (Clk_t/ and Clk_b), the DQS signals may be provided as a differential pair of data strobe signals (DQS_t/ and DQS_b) to provide differential pair signaling during reads and writes. For certain memory devices, such as a DDR5 SDRAM memory device, the differential pairs of DQS signals may be divided into upper and lower data strobe signals (e.g., UDQS_t/ and UDQS_b; LDQS_t/ and LDQS_b) corresponding to upper and lower bytes of data sent to and from the memory device 10, for instance. In some embodiments, as discussed below, the IO interface 16 may include phase divider circuitry 48 that splits the DQS signal into multiple (e.g., 4) phases. The IO interface 16 may also include phase detection circuitry to detect which phase receives a first pulse when sets of pulses on the DQS pin occur too frequently to enable the clock input circuit 18 to reset between sets of pulses.
An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the IO interface 16. The ZQ calibration signal may be provided to a reference pin and used to tune output drivers and ODT values by adjusting pull-up and pull-down resistors of the memory device 10 across changes in process, voltage and temperature (PVT) values. Because PVT characteristics may impact the ZQ resistor values, the ZQ calibration signal may be provided to the ZQ reference pin to be used to adjust the resistance to calibrate the input impedance to known values. As will be appreciated, a precision resistor is generally coupled between the ZQ pin on the memory device 10 and GND/VSS external to the memory device 10. This resistor acts as a reference for adjusting internal ODT and drive strength of the IO pins.
In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the IO interface 16. The loopback signal may be used during a test or debugging phase to set the memory device 10 into a mode wherein signals are looped back through the memory device 10 through the same pin. For instance, the loopback signal may be used to set the memory device 10 to test the data output (DQ) of the memory device 10. Loopback may include both a data and a strobe or possibly just a data pin. This is generally intended to be used to monitor the data captured by the memory device 10 at the IO interface 16.
As will be appreciated, various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (to define various modes of programmable operations and configurations), read/write amplifiers (to amplify signals during read/write operations), temperature sensors (for sensing temperatures of the memory device 10), etc., may also be incorporated into the memory device 10. Accordingly, it should be understood that the block diagram of
As illustrated, the multi-phase generation circuitry 50 uses the internal DS signal 54 and/or the internal DS false signal to divide the signal out using a toggle flip-flop 60 that toggles its output each time a pulse occurs on the internal DS signal 54. The multi-phase generation circuitry 50 also includes a latch 62 that latches the output from the toggle flip-flop 60 to track falling edges of the internal DS signal 54. In other words, the toggle flip-flop 60 sets a rising mode that causes changes of states in rising edge flip-flops 64 and/or 66 on rising edges of the internal DS signal 54. Moreover, the toggle flip-flop 60 and the latch 62 work together to set a falling mode that causes changes of state in falling edge flip-flops 68 and/or 70 during a falling edge of the internal DS signal 54.
DS0 72 corresponds to an output of the rising edge flip-flop 64. DS0 72 transitions high with every other rise of the external DQS signal 51. DS360 74 corresponds to a rising edge flip-flop 66. DS360 74 transitions high on rising edges of the external DQS signal 51 between those causing DS0 72 to go high. In other words, rising edges of the external DQS signal 51 alternate between causing DS0 72 and DS360 to go high.
DS180 76 corresponds to an output of the falling edge flip-flop 68. Due to the use of the internal DS false signal 56, DS180 76 transitions high with every other falling edge of the external DQS signal 51. Similarly, DS540 78 corresponds to an output of the falling edge flip-flop 70 and transitions high with the other alternating falling edges of the external DQS signal 51. In other words, DS0 72, DS360 74, DS180 76, and DS540 78 are each half-frequency signals transitioning high when a corresponding rising edge or falling edge of the external DQS signal 51 is received.
A falling edge 112 of the waveform 102 causes a rise 114 of the waveform 110. Similarly, a rising edge 116 of the waveform 102 causes a rise 118 of the waveform 104. Likewise, a falling edge 120 of the waveform 102 causes a rise 122 of the waveform 106, and a rising edge 124 of the waveform 102 causes a rise 126 of the waveform 108. A falling edge 128 of the waveform 102 causes another rise 130 of the waveform 110.
Since, in some embodiments, a write command always accompanies a start of the external DQS signal 51, the write command may be used as a reference for the external DQS signal 51.
Data on the DS 222 may be delayed by delays 224 and/or be amplified by amplifiers 226. The delays 224 may include a string of delays to coordinate the DS 222 with other signals, such as a WrStart 228 that indicates that a write command may be started to start counting the next data on DS 222. To do this count, the circuitry 220 uses the flip-flop 192 (of
Using FirstCnt 238 from multiple instances of the circuitry 220, the memory device 10 may determine which instances of the circuitry 220 have received data on DS 222 first. To perform this determination, the memory device 10 may include a phase detector 250, as illustrated in
At a next time 316 with the write start signal 302 transitioning high, the second DS signal 306 transitions high before the first DS signal 304. Accordingly, the second count signal 310 transitions high before the first count signal 308. However, since the first count signal 308 may clock the flip-flop 260, a change in the leading signal 312 does not occur until the first count signal 308 pulses at time 318. Thus, using the first count signal 308 as a clock for the flip-flop 260 may cause a delay 320 (e.g., ½ cycle) from the second count signal 310 transitioning high and phase detection propagation to the leading signal 312 when clock cycles into DS 222 are not in an even number and the phase detector 252 does not have sufficient time to reset between DS pulses.
An output, a_FirstCnt180QF 346, of the flip-flop 336 transitions high when FirstCnt540 334 is high and when the FirstCnt180 332 is high. Similarly, an output, a_FirstCnt540QF 348, of the flip-flop 338 transitions high when FirstCnt180 332 is high and when the FirstCnt540 334 is high. The phase detector 330 includes a keeper flip-flop 350 that keeps an output 352 of the phase detector 330 to a state using a_LookFor540lead 354. The a_LookFor540lead 354 is a pointer that when set high allows a_FirstCnt540QF 348 to immediately pass to the output 352 when a_FirstCnt540QF 348 is asserted (e.g., goes low). Until a_FirstCnt540QF 348 is asserted, a_LookFor540lead 354 will keep the output 352 at a high state indicating that DS180 76 occurs before DS540 78 in the current burst.
After a_FirstCnt540QF 348 is asserted and is immediately passed through to the output 352, the keeper flip-flop 350 will continue to hold a_LookFor540lead 354 high until a_FirstCnt180QF 346 is deasserted by FirstCnt180 332 firing. Then the state of a_FirstCnt180QF 346 is combined with the low state of a_FirstCnt540QF 348 to assert a set pin on the keeper flip-flop 350 to reset a_LookFor540lead 354 to low.
Since a_LookFor540lead 354 is then low, this setting allows the a_FirstCnt180QF 346 to immediately pass through to the output 352 when a_FirstCnt180QF 346 is asserted (e.g., goes low). Until a_FirstCnt180QF 346 is asserted, a_LookFor540lead 354 being low will keep the output 352 in a low state, which indicates that DS180 76 occurs after DS540 78 in the current burst.
After a_FirstCnt180QF 346 is asserted and is immediately passed through to the output 352, the keeper flip-flop 350 will continue to hold a_LookFor540lead 540 low until a_FirstCnt540QF 348 is deasserted (e.g., transitions high) by FirstCnt540 334 firing after the FirstCnt180 332 first fired in the current burst. The state of the a_FirstCnt540QF 348 is combined with the low state of a_FirstCnt180QF 346 in gate 356 to assert the reset pin of the keeper flip-flop 350 to set a_LookFor540lead 354 back to high.
Although the foregoing embodiments include assertions that are logic lows or logic highs, the assertions may be in a logically opposite position in some embodiments. For example, NAND gates and/or inverters may be replaced in some embodiments.
The foregoing discussion assumes a set length (e.g., 1 cycle) of a write preamble, but some memory devices may utilize programmable write preamble lengths.
Similarly, when a second preamble length (e.g., 2) is set, the write at the write time 426 causes a second write launch 432 and a corresponding DQS launch 434. Moreover, when a third preamble length (e.g., 3) is set, the write at the write time 426 causes a third write launch 436 and a corresponding third DQS launch 438. With the second or third preamble lengths, a falling edge 440 of the external DQS 424, the write is captured and counting begins.
The delay circuitry 456 also includes a delayed route that adds delays for long write preamble lengths. For example, the delay circuitry 456 may include a flip-flop 478 that receives the output 472 and delays the output for one cycle of the clock. In other words, the output 472 may be delayed from a clock edge used to pass the output 472 through the flip-flop 192 by using the next clock cycle of the clock to gate the output 472 using the flip-flop 478. Furthermore, in some embodiments, additional flip-flops may be used to add additional cycles of delay to provide additional possible preamble length (e.g., 4) timings. These additional flip-flops may be arranged in a chain that receives the output of the flip-flop with each of the additional flip-flops using the same clock as the flip-flop 192 with the output of each flip-flop passed to the selector 460 (e.g., in a same multiplexor or in a chain of multiplexors). The flip-flop 478 (and additional flip-flops) may be reset using a reset signal 480 from the selection circuitry 458.
The selector 460 receives a preamble stage 484 that indicates whether to delay the output with the delay circuitry 456 or to bypass the delay circuitry 456. In some embodiments, when the preamble stage 484 is high, the delay circuitry 456 is utilized. Otherwise, the delay circuitry 456 is bypassed. In embodiments with additional possible stages, the preamble stage 484 may include more than a single binary bit, such as an encoded bit stream or multiple lines. In some embodiments, a preamble stage false 486 may be used as a complement to the preamble stage 484 to ensure that the preamble stage 484 is interpreted properly. As illustrated in
The selection circuitry 458 receives the CntRstF 234 and the WrPre 454. The CntRstF 234 sets whether the count is to be reset. WrPre 454 indicates whether (and/or how many) delay circuitries to delay in the delay circuitry 456 based on the write preamble length if the phase including the circuitry 450 captures the write command before the corresponding other phase. For example, as illustrated, if only one delay (e.g., flip-flop 478) is included WrPre 454 may indicate whether the delay should be used or bypassed. If more than a single delay is used, WrPre 454 may indicate a state corresponding to which delays are to be used.
CntRstF 234 may be inverted at inverter 490 and re-inverted at inverter 492 to produce the reset signal 480. CntRst 493 resulting from inversion at inverter 490 indicates whether a count is to be reset. The CntRst 493 and the WrPre 454 are submitted to a NOR gate 494 that resets a flip-flop 496 if the count is not to be reset and the preamble is a default value. The flip-flop 496 receives WrCmdCaptureOtherPhF 498 that indicates that another phase has not captured a write command. The flip-flop 496 clocks WrCmdCaptureOtherPhF 498 using WrCmdCapture 236 for the current phase and/or its complementary WrCmdCaptureF 500. The flip-flop 496 then outputs the preamble stage 484 asserting when the delay circuitry 456 is to be used. The selection circuitry 458 also includes an inverter 502 to produce the complementary preamble stage false 486 for transport to the selector 460.
Although the foregoing discusses various logic-low and/or logic-high assertion polarities, at least some of these polarities may be inverted in some embodiments. Furthermore, in some embodiments, logic gates as discussed herein may be replaced with similar logical functions, such as an inverter replaced with a single NAND gate or other similar changes.
While the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the following appended claims.
The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function] . . . ” or “step for [perform]ing [a function] . . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).