MEMORY DEVICE AND OPERATING METHOD THEREOF
First Claim
1. A memory device comprising:
- a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines;
a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and
control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.
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Accused Products
Abstract
A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.
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Citations
21 Claims
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1. A memory device comprising:
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a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 16, 17)
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11. A method for operating a memory device including a plurality of memory cells respectively coupled to a plurality of word lines, the method comprising:
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performing at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and while the program voltage is being applied to the selected word line, applying program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and applying a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells. - View Dependent Claims (12, 13, 14, 15, 18, 19)
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20. A memory device comprising:
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a plurality of memory cells coupled to a word line; a peripheral circuit configured to perform a shadow program operation or a normal program operation on the plurality of memory cells; and control logic configured to control the peripheral circuit to perform the shadow program operation on some memory cells among the plurality of memory cells and perform the normal program operation on the other memory cells among the plurality of memory cells, wherein the normal program operation is configured to program memory cells to be in, as a target program state, a program state corresponding to a program voltage applied to the word line, and the shadow program operation is configured to simultaneously program memory cells to be in, as a target program state, a program state corresponding to the program voltage applied to the word line and program memory cells to be in, as a target program state, a program state different from that corresponding to the program voltage.
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21. A memory device comprising:
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first and second groups of memory cells coupled to a selected word line; and a program circuit configured to; program the first group to be in corresponding target program states by applying program voltages to the selected word line; and simultaneously program, in the second group, a memory cell to be in a first target program state by applying the program voltages and remaining memory cells to be in corresponding target program states different from the first target program state.
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Specification