SENSE AMPLIFIER WITH LOWER OFFSET AND INCREASED SPEED

• US 20190325941A1
• Filed: 04/19/2018
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Guo, Xinwei, Vimercati, Daniele
• Granted Patent: US 10,446,220 B1
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2253 Address circuits or decoders
• CPC Class Codes: G11C 11/2255 Bit-line or column circuits
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.

Claims

1. A method, comprising:

configuring an amplifier component to operate in an amplifier mode during a first pre-charging portion of a read operation based at least in part on activating or deactivating a second switching component in the amplifier component;

coupling, while the amplifier component is operating in the amplifier mode, a first voltage source with a first input of the amplifier component, a first output of the amplifier component with a second input of the amplifier component, and the first output of the amplifier component with a digit line to pre-charge the digit line to a first voltage during the first pre-charging portion of the read operation;

coupling, during a signal development portion of the read operation of a memory cell, a ferroelectric capacitor of the memory cell with the digit line associated with the memory cell to adjust an amount of electric charge on the digit line;

coupling, during the signal development portion, the first input of the amplifier component with the digit line to amplify a voltage of the digit line;

decoupling, after the signal development portion of the read operation, the first input of the amplifier component from the digit line;

configuring the amplifier component to operate in a latch mode based at least in part on activating or deactivating a first switching component in the amplifier component; and

outputting, on the first output of the amplifier component, a state of the memory cell while the amplifier component operates in the latch mode, wherein the first pre-charging portion of the read operation occurs before the signal development portion of the read operation.

3. The method of claim 1, further comprising:

coupling, during a second pre-charging portion of the read operation, a second voltage source with the digit line to adjust the voltage of the digit line to a second voltage; and

decoupling the second voltage source from the digit line after the voltage of the digit line has been adjusted to the second voltage during the second pre-charging portion, wherein the second pre-charging portion occurs before the first pre-charging portion.

4. The method of claim 1, further comprising:

configuring the amplifier component to operate in the amplifier mode at least in part by activating or deactivating a third switching component in the amplifier component before coupling the first input of the amplifier component to the digit line during the signal development portion of the read operation, wherein configuring the amplifier component to operate in the amplifier mode comprises configuring the amplifier component to amplify a difference between a predetermined voltage supplied by the first voltage source and the voltage of the digit line.

5. The method of claim 1, wherein configuring the amplifier component to operate in the amplifier mode during the first pre-charging portion of the read operation comprises configuring the amplifier component to generate the first voltage based at least in part on a predetermined voltage and a voltage offset of the amplifier.

6. The method of claim 1, wherein configuring the amplifier component to operate in the amplifier mode comprises configuring first and second transistors in the amplifier component to operate as a current mirror based at least in part on coupling a gate of a first transistor in the amplifier component to a gate of a second transistor in the amplifier component.

7. The method of claim 4, further comprising:

coupling, during the signal development portion, a second output of the amplifier component to an amplifier capacitor that is coupled with the digit line, wherein operating the amplifier component in the amplifier mode during the signal development portion comprises integrating the amount of electric charge on the digit line using the amplifier component and the amplifier capacitor.

8. The method of claim 7, wherein configuring the amplifier component to operate in the latch mode comprises:

decoupling the second output of the amplifier component from the amplifier capacitor; and

coupling the second input of the amplifier component to the amplifier capacitor, wherein operating the amplifier component in the latch mode comprises the amplifier component determining the state based at least in part on a comparison of a voltage of the amplifier capacitor with a reference voltage and latching the state.

9. The method of claim 8, wherein the amplifier component latches the state by storing the state using a plurality of transistors in the amplifier component, and wherein the amplifier component amplifies the voltage of the digit line using at least some of the plurality of transistors.

10. The method of claim 8, wherein the state may be a first state or a second state, wherein the amplifier component latches the first state by storing the first state using a plurality of transistors in the amplifier component, and wherein the amplifier component latches the second state by providing the second state to a separate latch circuit coupled with the amplifier component.

2. (canceled)

11. An apparatus, comprising:

an amplifier capacitor coupled with a digit line associated with a memory cell; and

an amplifier component configured to be selectively coupled with the digit line and with the amplifier capacitor, the amplifier component comprising;

a plurality of transistors, and

a plurality of switching components configured to select a mode of the amplifier component by activating one or more electrical connections between respective transistors,

the plurality of switching components configured to select the mode as an amplifier mode that configures the amplifier component to, while an input of the amplifier component is coupled with the digit line and an output of the amplifier component is coupled with the amplifier capacitor, adjust a voltage of the amplifier capacitor, and

the plurality of switching components configured to select the mode as a latch mode that configures the amplifier component to latch a state of the memory cell in response to an activation signal, wherein the plurality of switching components are configured to select the mode as the amplifier mode which configures a first transistor of the plurality of transistors and a second transistor of the plurality of transistors to operate in a current mirror mode by activating an electrical connection between a gate of the first transistor and a gate of the second transistor.

12. The apparatus of claim 11, wherein the plurality of switching components are configured to select the mode as the latch mode which configures the amplifier component to determine, while a first input of the amplifier component is coupled with the amplifier capacitor, the state based on a comparison of the voltage of the amplifier capacitor with a reference voltage.

14. The apparatus of claim 11, wherein the plurality of switching components are configured to select the mode as the latch mode by deactivating the electrical connection between the gate of the first transistor of the plurality of transistors and the gate of the second transistor of the plurality of transistors.

15. The apparatus of claim 12, wherein the amplifier component is configured to latch the state by storing the state in the amplifier component using at least some of the plurality of transistors.

16. The apparatus of claim 12, further comprising:

a latch circuit configured to be selectively coupled with a first output of the amplifier component and to store the state, wherein the amplifier component is configured to latch the state, based at least in part on the determination of the state, by providing the state to the latch circuit.

17. The apparatus of claim 11, wherein when the plurality of switching components are configured to select the mode as the amplifier mode, the amplifier component is configured to adjust the voltage of the amplifier capacitor by amplifying a difference between a voltage of the digit line and a predetermined voltage using a set of transistors of the plurality of transistors, and wherein when the plurality of switching components are configured to select the mode as the latch mode the amplifier component is configured to latch the state using at least some of the set of transistors.

13. (canceled)

18. A memory device, comprising:

a memory cell;

a digit line configured to be selectively coupled with the memory cell;

an amplifier component configured to be selectively coupled with the digit line;

a controller to;

couple, during a first portion of a read operation of the memory cell, the amplifier component to the digit line;

couple, during the first portion, a ferroelectric capacitor of the memory cell with the digit line to adjust an amount of electric charge on the digit line;

decouple the amplifier component from the digit line after the first portion of the read operation;

configure the amplifier component to operate in a latch mode based at least in part on configuring a plurality of switching components in the amplifier component;

cause a state of the memory cell to be latched while the amplifier component is configured to operate in the latch mode;

configure the amplifier component to operate in an amplifier mode during a second portion of the read operation based at least in part on configuring the plurality of switching components in the amplifier component; and

couple, while the amplifier component is operating in the amplifier mode, a first input of the amplifier component with a second voltage source and an output of the amplifier component with the digit line to pre-charge the digit line to a first voltage during the second portion of the read operation,

wherein the second portion of the read operation occurs before the first portion of the read operation.

19. The memory device of claim 18, further comprising:

an amplifier capacitor coupled with the digit line and configured to be selectively coupled with the amplifier component,

wherein the controller is configured to configure the amplifier component to operate in the latch mode based at least in part on coupling the first input of the amplifier component to the amplifier capacitor and coupling a second input of the amplifier component to a first voltage source, and

wherein the controller is configured to cause the state to be latched based at least in part on activating the amplifier component while it is configured in the latch mode.

20. The memory device of claim 19, wherein the amplifier component is configured to determine, while the amplifier component is configured in the latch mode, the state based at least in part on a comparison of a voltage of the amplifier capacitor with a voltage of the first voltage source.

22. The memory device of claim 18, wherein the controller is further configured to:

during the first portion of the read operation;

couple the first input of the amplifier component with a third voltage source; and

couple the second input of the amplifier component with the digit line, wherein configuring the amplifier component to operate in the amplifier mode configures the amplifier component to, during the first portion of the read operation, amplify a difference between a voltage of the third voltage source and a voltage of the digit line.

23. The memory device of claim 22, wherein the controller causes the state to be latched based at least in part on activating the amplifier component while it is configured in the latch mode, which configures the amplifier component to latch the state using a plurality of transistors in the amplifier component, and wherein the amplifier component is configured to amplify the difference between the voltage of the third voltage source and the voltage of the digit line using at least some of the plurality of transistors.

24. The memory device of claim 18, wherein the first portion comprises a signal development portion of the read operation.

25. The memory device of claim 18, wherein the second portion comprises a pre-charging portion of the read operation.

21. (canceled)