Coupling Compensation Circuitry

• US 20190325948A1
• Filed: 04/23/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Nautiyal, Vivek, Gupta, Lalit, Bohra, Fakhruddin Ali, Dwivedi, Shri Sagar
• Granted Patent: US 10,600,477 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

Claims

1. An integrated circuit, comprising:

a bitcell coupled to a bitline;

a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver;

a first signal line coupled to a gate of the column multiplexer device that provides a first transition signal;

a second signal line coupled to an input of the write driver that provides a second transition signal, wherein the second transition signal is substantially similar to the first transition signal; and

a coupling device coupled between the first signal line and the second signal line.

2. The integrated circuit of claim 1, wherein the column multiplexer device comprises a transistor, and wherein the first signal line is coupled to the gate of the transistor.

3. The integrated circuit of claim 1, wherein the write driver comprises an inverter, and wherein the column multiplexer device is coupled to the bitline between the bitcell and the output of the inverter.

4. The integrated circuit of claim 1, wherein the first signal line comprises a write column multiplexer select signal line that is coupled to the gate of the column multiplexer device.

5. The integrated circuit of claim 1, wherein the second signal line comprises a write clock signal line that is coupled to the input of the write driver.

6. The integrated circuit of claim 1, wherein the coupling device is coupled between the gate of the column multiplexer device and the second signal line.

7. The integrated circuit of claim 1, wherein the coupling device comprises a capacitor.

8. The integrated circuit of claim 1, wherein the coupling device comprises a transistor that is coupled together to operate as a capacitor.

9. An integrated circuit, comprising:

a bitcell coupled to a bitline;

a column multiplexer device coupled to the bitline between the bitcell and an output of a sense amplifier;

a first signal line coupled to a gate of the column multiplexer device that provides a first transition signal;

a second signal line coupled to an output of a logic device that provides a second transition signal, wherein the second transition signal is substantially similar to the first transition signal; and

a coupling device coupled between the first signal line and the second signal line.

10. The integrated circuit of claim 9, wherein the column multiplexer device comprises a transistor, and wherein the first signal line is coupled to the gate of the transistor.

11. The integrated circuit of claim 9, wherein the first signal line comprises a read column multiplexer select signal line that is coupled to the gate of the column multiplexer device.

12. The integrated circuit of claim 9, wherein the second signal line comprises a bitline precharge signal line that is coupled to the output of the logic device.

13. The integrated circuit of claim 9, wherein the logic device comprises an inverter.

14. The integrated circuit of claim 9, wherein the coupling device is coupled between a gate of the column multiplexer device and the second signal line.

15. The integrated circuit of claim 9, wherein the coupling device comprises a capacitor.

16. The integrated circuit of claim 9, wherein the coupling device comprises a transistor that is coupled together to operate as a capacitor.

17. An integrated circuit, comprising:

a bitcell coupled to a bitline;

read and write circuitry having a first column multiplexer device and a second column multiplexer device, wherein the first column multiplexer device is coupled to the bitline between the bitcell and a write driver, and wherein the second column multiplexer device is coupled to the bitline between the bitcell and a sense amplifier;

multiple signal lines including a first signal line, a second signal line, a third signal line, and a fourth signal line, wherein the first signal line is coupled to a gate of the first column multiplexer device and provides a first transition signal, wherein the second signal line is coupled to the write driver and provides a second transition signal that is substantially similar to the first transition signal, wherein the third signal line is coupled to a gate of the second column multiplexer device and provides a third transition signal, and wherein the fourth signal line is coupled to a logic device and provides a fourth transition signal that is substantially similar to the third transition signal; and

multiple coupling devices including a first coupling device and a second coupling device, wherein the first coupling device is coupled between the first signal line and the second signal line, and wherein the second coupling device is coupled between the third signal line and the fourth signal line.

18. The integrated circuit of claim 17, wherein the first coupling device is coupled between the gate of the first column multiplexer device and the second signal line, and wherein the second coupling device is coupled between the gate of the second column multiplexer device and the fourth signal line.

19. The integrated circuit of claim 17, wherein the first coupling device comprises a first capacitor, and wherein the second coupling device comprises a second capacitor.

20. The integrated circuit of claim 17, wherein the first coupling device comprises a first transistor that is coupled together to operate as a first capacitor, and wherein the second coupling device comprises a second transistor that is coupled together to operate as a second capacitor.