Integrated Circuit Using Discharging Circuitries for Bit Lines

• US 20190325949A1
• Filed: 04/23/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Gupta, Lalit, Dasani, Jitendra, Nautiyal, Vivek, Dwivedi, Shri Sagar, Bohra, Fakhruddin Ali
• Granted Patent: US 10,878,892 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

Claims

1. An integrated circuit, comprising:

a memory array comprising a plurality of memory cells, wherein the memory cells are arranged into a plurality of columns and are configured to be accessed using a plurality of bit line pairs; and

a plurality of discharging circuitries configured to selectively discharge the plurality of bit line pairs, wherein a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells, and wherein the respective discharging circuitry comprises;

a first circuitry configured to discharge a bit line pair of the respective column of memory cells to a first voltage when the bit line pair is selected for a memory operation; and

a second circuitry configured to discharge the bit line pair of the respective column of memory cells to a second voltage when the bit line pair is not selected for a memory operation, wherein the second voltage is greater than the first voltage.

2. The integrated circuit of claim 1, wherein the negative supply voltage node of the respective column is coupled to each negative supply voltage node of the memory cells of the column.

3. The integrated circuit of claim 1, wherein the first circuitry and the second circuitry are coupled in parallel, and wherein only one of the first circuitry and the second circuitry may be active.

4. The integrated circuit of claim 1, wherein the respective discharging circuitry has one end coupled to the negative supply voltage node of the respective column and another end coupled to an external power supply ground node.

5. The integrated circuit of claim 1 wherein the first circuitry comprises an NMOS transistor configured to receive a column select signal at its gate, wherein the column select signal is high when the bit line pair of the respective column is selected.

6. The integrated circuit of claim 1, wherein the first circuitry is configured to couple the negative supply voltage node of the respective column to an external negative supply voltage node when the bit line pair of the respective column is selected.

7. The integrated circuit of claim 6, wherein the first circuitry is configured to discharge the bit line pair via a current flowing from the bit line pair to the external negative supply voltage node.

8. The integrated circuit of claim 6, wherein the negative supply voltage node of the respective column is driven to a voltage level that is substantially equal to a voltage level of the external negative supply voltage node when the bit line pair is selected.

9. The integrated circuit of claim 1, wherein the second circuitry comprises an NMOS transistor coupled in series with an NMOS diode device.

10. The integrated circuit of claim 9, wherein the NMOS diode device is configured to have a drain coupled to the negative supply voltage node of the respective column and a source couple to an external negative supply voltage node when the bit line pair is not selected.

11. The integrated circuit of claim 9, wherein the NMOS transistor is configured to receive a complementary column select signal at its gate, and wherein the complementary column select signal is high when the bit line pair is not selected.

12. The integrated circuit of claim 9, wherein the NMOS diode device is configured to drive a voltage level of the negative supply voltage node of the respective column toward a threshold voltage of the NMOS diode device when the bit line pair is not selected.

13. The integrated circuit of claim 12, wherein the voltage level of the negative supply voltage node of the respective column is less than or equal to the threshold voltage of the NMOS diode device when the bit line pair is not selected.

14. The integrated circuit of claim 12, wherein the voltage level of the negative supply voltage node of the respective column increases for every memory operation in which the bit line pair is not selected.

15. The integrated circuit of claim 12, wherein the bit line pair is configured to discharge an amount of voltage that is less than or equal to the threshold voltage when the bit line pair is not selected.

16. The integrated circuit of claim 1, wherein the discharge circuitry is configured to receive a high column select signal prior to a word line activation if a voltage level of the negative supply voltage node is greater than zero.

17. An integrated circuit, comprising:

a memory array comprising a plurality of memory cells, wherein the memory cells are arranged into a plurality of columns and are configured to be accessed using a plurality of bit line pairs; and

a diode device; and

a plurality of discharging circuitries configured to selectively discharge the plurality of bit line pairs, wherein a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells, and wherein the respective discharging circuitry comprises;

a first circuitry configured to discharge a bit line pair of the respective column of memory cells to a first voltage when the bit line pair is selected for a memory operation, wherein the first circuitry comprises a first transistor device; and

a second circuitry configured to discharge the bit line pair of the respective column of memory cells to a second voltage when the bit line pair is not selected for a memory operation, wherein the second circuitry comprises a second transistor device coupled in series to the diode device, wherein the second voltage is greater than the first voltage.

18. The integrated circuit of claim 17, wherein:

the diode device is configured to drive a voltage level of the negative supply voltage node of the respective column toward an averaged threshold voltage of the diode device when the bit line pair is not selected; and

the bit line pair is configured to discharge an amount of voltage that is less than or equal to the averaged threshold voltage when the bit line pair is not selected.

19. An integrated circuit, comprising:

a first memory array comprising a plurality of first memory cells, wherein the first memory cells are arranged into a plurality of first columns and are configured to be accessed using a plurality of first bit line pairs;

a second memory array comprising a plurality of second memory cells, wherein the second memory cells are arranged into a plurality of second columns and are configured to be accessed using a plurality of second bit line pairs;

a plurality of discharging circuitries configured to selectively discharge the plurality of first and second bit line pairs, wherein a respective discharging circuitry is coupled to a first negative supply voltage node of a respective column of first memory cells and a second negative supply voltage node of a respective column of second memory cells, and wherein the respective discharging circuitry comprises;

a first circuitry configured to discharge a first bit line pair of the respective column of first memory cells and a second bit line pair of the respective column of second memory cells to a first voltage when the first bit line pair and the second bit line pair are selected for memory operations; and

a second circuitry configured to discharge the first bit line pair of the respective column of first memory cells and the second bit line pair of the respective column of second memory cells to a second voltage when the first bit line pair and the second bit line pair are not selected for the memory operations, wherein the second voltage is greater than the first voltage.

20. The integrated circuit of claim 19, wherein the first circuitry comprises a first transistor device, and wherein the second circuitry comprises a second transistor device coupled in series to a diode device.