TERNARY MEMORY CELL AND TERNARY MEMORY CELL ARRANGEMENT

• US 20190325963A1
• Filed: 04/23/2018
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Ferroelectric Memory GmbH
• Original Assignee: Ferroelectric Memory GmbH
• Inventors: Noack, Marko
• Granted Patent: US 10,650,892 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

In various embodiments, a ternary memory cell is provided, the ternary memory cell including: a first ferroelectric memory cell and a second ferroelectric memory cell in a parallel or serial arrangement, wherein each of the first ferroelectric memory cell and the second ferroelectric memory cell is switchable into a first ferroelectric memory cell state and a second ferroelectric memory cell state; and wherein a first matching state is defined by the first ferroelectric memory cell in the first ferroelectric memory cell state and the second ferroelectric memory cell in the second ferroelectric memory cell state, wherein a second matching state is defined by the first ferroelectric memory cell in the second ferroelectric memory cell state and the second ferroelectric memory cell in the first ferroelectric memory cell state, and wherein a third matching state is defined by the first ferroelectric memory cell and the second ferroelectric memory cell being in the same ferroelectric memory cell state.

Claims

1. A ternary memory cell comprising:

a first remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control an electrical behavior of the first terminal and the second terminal of the first remanent-polarizable memory cell;

a second remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control an electrical behavior of the first terminal and the second terminal of the second remanent-polarizable memory cell;

a first match line node and a second match line node to connect the ternary memory cell to a first match line and a second match line respectively; and

a first lookup node and a second lookup node to connect the ternary memory cell to a first lookup line and a second lookup line respectively,

wherein the first terminal of the first remanent-polarizable memory cell and the first terminal of the second remanent-polarizable memory cell are electrically connected to the first match line node and wherein the second terminal of the first remanent-polarizable memory cell and the second terminal of the second remanent-polarizable memory cell are electrically connected to the first match line node, and

wherein the control terminal of the first remanent-polarizable memory cell is electrically connected to the first lookup node and wherein the control terminal of the second remanent-polarizable memory cell is electrically connected to the second lookup node.

2. The ternary memory cell of claim 1,

wherein the first remanent-polarizable memory cell comprises a first memory state and a second memory state and wherein the second remanent-polarizable memory cell comprises a first memory state and a second memory state.

3. The ternary memory cell of claim 2,

wherein the ternary memory cell comprises three matching states generated by distinct combinations of the first memory state and the second memory state of the first remanent-polarizable memory cell and the first memory state and the second memory state of the second remanent-polarizable memory cell.

4. The ternary memory cell of claim 2,

wherein a first matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the first memory state and the second remanent-polarizable memory cell in the second memory state,

wherein a second matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the second memory state and the second remanent-polarizable memory cell in the first memory state, and

wherein a third matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the second memory state and the second remanent-polarizable memory cell in the second memory state.

5. The ternary memory cell of claim 2,

wherein, in the first memory state, the first remanent-polarizable memory cell is configured to

electrically isolate the first match line node and the second match line node from one another in the case that a first lookup voltage is applied to the first lookup node and

provide a conductive path between the first match line node and the second match line node in the case that a second lookup voltage is applied to the first lookup node;

and,

wherein, in the second memory state, the first remanent-polarizable memory cell is configured to

electrically isolate the first match line node and the second match line node from one another in the case that the first lookup voltage is applied to the first lookup node and in the case that the second lookup voltage is applied to the first lookup node.

6. The ternary memory cell of claim 5,

wherein, in the first memory state, the second remanent-polarizable memory cell is configured to

electrically isolate the first match line node and the second match line node from one another in the case that the first lookup voltage is applied to the second lookup node and

provide a conductive path between the first match line node and the second match line node in the case that the second lookup voltage is applied to the second lookup node;

and,

wherein, in the second memory state, the second remanent-polarizable memory cell is configured to electrically isolate the first match line node and the second match line node from one another in the case that the first lookup voltage is applied to the second lookup node and in the case that the second lookup voltage is applied to the second lookup node.

7. The ternary memory cell of claim 5,

wherein each of the first remanent-polarizable memory cell and the second remanent-polarizable memory cell comprises a first threshold voltage associated with the first memory state and a second threshold voltage associated with the second memory state.

8. The ternary memory cell of claim 7,

wherein the first lookup voltage is less than the first threshold voltage and wherein the second lookup voltage is equal to or greater than the first threshold voltage and less the than second threshold voltage.

9. A ternary memory cell comprising:

a first match line node, a second match line node, a first lookup node, and a second lookup node;

a first remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control the electrical behavior of the first terminal and the second terminal of the first remanent-polarizable memory cell; and

a second remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control the electrical behavior of the first terminal and the second terminal of the second remanent-polarizable memory cell,

wherein the first terminal of the first remanent-polarizable memory cell is electrically connected to the first match line node, wherein the second terminal of the second remanent-polarizable memory cell is electrically connected to the second match line node, and wherein the second terminal of the first remanent-polarizable memory cell and the first terminal of the second remanent-polarizable memory cell are electrically connected with one another, and

wherein the control terminal of the first remanent-polarizable memory cell is electrically connected to the first lookup node and wherein the control terminal of the second remanent-polarizable memory cell is electrically connected to the second lookup node.

10. The ternary memory cell of claim 9,

wherein the first remanent-polarizable memory cell comprises a first memory state and a second memory state and wherein the second remanent-polarizable memory cell comprises first memory state and a second memory state.

11. The ternary memory cell of claim 10,

wherein the ternary memory cell comprises three matching states generated by distinct combinations of the first memory state and the second memory state of the first remanent-polarizable memory cell and the first memory state and the second memory state of the second remanent-polarizable memory cell.

12. The ternary memory cell of claim 11,

wherein a first matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the second memory state and the second remanent-polarizable memory cell in the first memory state,

wherein a second matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the first memory state and the second remanent-polarizable memory cell in the second memory state, and

wherein a third matching state of the ternary memory cell comprises the first remanent-polarizable memory cell in the second memory state and the second remanent-polarizable memory cell in the second memory state.

13. The ternary memory cell of claim 11,

wherein, in the first memory state, the first remanent-polarizable memory cell is configured to allow a current flow between its first terminal and second terminal in the case that a first lookup voltage is applied to the first lookup node and in the case that a second lookup voltage is applied to the first lookup node, and,

wherein, in the second memory state, the first remanent-polarizable memory cell is configured to

prevent a current flow between its first terminal and second terminal in the case that the first lookup voltage is applied to the first lookup node and

allow a current flow between its first terminal and second terminal in the case that the second lookup voltage is applied to the first lookup node.

14. The ternary memory cell of claim 13,

wherein, in the first memory state, the second remanent-polarizable memory cell is configured to allow a current flow between its first terminal and second terminal in the case that the first lookup voltage is applied to the second lookup node and in the case that the second lookup voltage is applied to the second lookup node, and,

wherein, in the second memory state, the second remanent-polarizable memory cell is configured to

prevent a current flow between its first terminal and second terminal in the case that the first lookup voltage is applied to the second lookup node and

allow a current flow between its first terminal and second terminal in the case that the second lookup voltage is applied to the second lookup node.

15. The ternary memory cell of claim 13,

wherein each of the first remanent-polarizable memory cell and the second remanent-polarizable memory cell comprises a first threshold voltage associated with the first memory state and a second threshold voltage associated with the second memory state.

16. The ternary memory cell of claim 15,

wherein the first lookup voltage is equal to or greater than the first threshold voltage and that the second lookup voltage is equal to or greater than the second threshold voltage.

17. A ternary memory cell arrangement comprising:

a plurality of ternary memory cells, each ternary memory cell of the plurality of ternary memory cells is switchable into a first matching state, a second matching state, and a third matching state, wherein each ternary memory cell of the plurality of ternary memory cells comprises;

a first ferroelectric memory cell and a second ferroelectric memory cell in a parallel or serial arrangement, wherein each of the first ferroelectric memory cell and the second ferroelectric memory cell is switchable into a first ferroelectric memory cell state and a second ferroelectric memory cell state; and

wherein the first matching state is defined by the first ferroelectric memory cell in the first ferroelectric memory cell state and the second ferroelectric memory cell in the second ferroelectric memory cell state, wherein the second matching state is defined by the first ferroelectric memory cell in the second ferroelectric memory cell state and the second ferroelectric memory cell in the first ferroelectric memory cell state, and wherein the third matching state is defined by the first ferroelectric memory cell and the second ferroelectric memory cell being in the same ferroelectric memory cell state.

18. The ternary memory cell arrangement of claim 17,

wherein, in the case of the parallel arrangement, each ferroelectric memory cell of the corresponding first subset is configured to

in the first ferroelectric memory cell state, electrically conductively connect the first match line to the second match line in the case that a second lookup voltage is applied to a corresponding control terminal of the ferroelectric memory cell and electrically isolate the first match line from the second match line in the case that a first lookup voltage is applied to the corresponding control terminal, and

in the second ferroelectric memory cell state, electrically isolate the first match line from the second match line for both cases either if the first lookup voltage or the second lookup voltage is applied to the corresponding control terminal.

19. The ternary memory cell arrangement of claim 17,

wherein, in the case of the serial arrangement, each ferroelectric memory cell of the corresponding first subset is configured to

in the second ferroelectric memory cell state, electrically conductively connect the first match line to the second match line in the case that a second lookup voltage is applied to a corresponding control terminal of the ferroelectric memory cell and electrically isolate the first match line from the second match line in the case that a first lookup voltage is applied to the corresponding control terminal, and,

in the second ferroelectric memory cell state, electrically conductively connect the first match line to the second match line for both cases either if the first lookup voltage or the second lookup voltage is applied to the corresponding control terminal.

20. The ternary memory cell arrangement of claim 17, further comprising:

a lookup circuit coupled to a plurality of lookup line drivers and configured to send a lookup word to a plurality of first subsets of the plurality of ternary memory cells, each first subset of the plurality of first subsets defines a corresponding stored word; and

an address encoder coupled to a plurality of match line drivers and configured to output an address signal associated with a match or mismatch of the lookup word with the corresponding stored word of each of the plurality of first subsets.