Three-dimensional Vertical NOR Flash Thin-Film Transistor Strings
First Claim
1. A memory structure, comprising:
- a storage transistor having a charge storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of charge stored in the charge storage region;
a word line connected to the gate terminal to provide a control voltage during a read operation;
a bit line connecting the first drain or source terminal to data detection circuitry; and
a source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.
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Accused Products
Abstract
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.
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Citations
49 Claims
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1. A memory structure, comprising:
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a storage transistor having a charge storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of charge stored in the charge storage region; a word line connected to the gate terminal to provide a control voltage during a read operation; a bit line connecting the first drain or source terminal to data detection circuitry; and a source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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Specification