NONVOLATILE MEMORY APPARATUS AND OPERATING METHOD OF THE NONVOLATILE MEMORY APPARATUS
First Claim
1. A nonvolatile memory apparatus comprising:
- a first memory cell array including a plurality of first memory cells coupled between a first of first word lines and a bit line;
a second memory cell array including a plurality of second memory cells coupled between a plurality of second word lines and the bit line; and
a data sensing circuit configured to define a sensing period and a latch period based on a power-up signal, to precharge a sensing node coupled to the bit line, to amplify a voltage level of the sensing node during the sensing period, and to generate an output signal by latching the amplified signal during the latch period.
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Abstract
A nonvolatile memory apparatus may include a first memory cell array, a second memory cell array, and a data sensing circuit. The first memory cell array may include a plurality of first memory cells coupled between a plurality of first word lines and a bit line. The second memory cell array may include a plurality of second memory cells coupled between a plurality of second word lines and the bit line. The data sensing circuit may define a sensing period and a latch period based on a power-up signal, may precharge a sensing node coupled to the bit line, may sense and amplify a voltage level of the sensing node, during the sensing period, and may generate an output signal by latching the sensed and amplified signal during the latch period.
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Citations
17 Claims
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1. A nonvolatile memory apparatus comprising:
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a first memory cell array including a plurality of first memory cells coupled between a first of first word lines and a bit line; a second memory cell array including a plurality of second memory cells coupled between a plurality of second word lines and the bit line; and a data sensing circuit configured to define a sensing period and a latch period based on a power-up signal, to precharge a sensing node coupled to the bit line, to amplify a voltage level of the sensing node during the sensing period, and to generate an output signal by latching the amplified signal during the latch period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An operating method of a nonvolatile memory apparatus comprising a first memory cell array coupled to a sensing node through a bit line, the operating method comprising:
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generating a sensing enable signal based on a power-up signal; generating an amplification signal by comparing a voltage level of the sensing node with a reference voltage based on the sensing enable signal; generating a latch enable signal, which is enabled within an enable period of the sensing enable signal; and generating an output signal by latching the amplification signal based on the latch enable signal. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification