DATA STORAGE APPARATUS AND METHOD FOR PREVENTING DATA ERROR USING THE SAME

• US 20190325981A1
• Filed: 04/18/2019
• Published: 10/24/2019
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: CHENG, Yu-Hsuan
• Granted Patent: US 10,714,193 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

Claims

1. A data storage apparatus, comprising:

a memory, comprising a plurality of blocks; and

a memory controller coupled to the memory and configured to perform the following operations;

recording a read count of a target block of the memory;

performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and

programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

2. The data storage apparatus according to claim 1, wherein the target block comprises a plurality of pages or a plurality of sectors, and the read count of the target block indicates the sum of the read count of respective page or sector of the target block.

3. The data storage apparatus according to claim 1, wherein when determining whether the read count of the target block meets the condition, the determination is based on whether the read count of the target block is over a threshold value.

4. The data storage apparatus according to claim 1, wherein when performing the error bit check, the memory controller reads a page or sector of the free storage space and determines whether a read result comprises a default value.

5. The data storage apparatus according to claim 1, wherein when performing the error bit check, the memory controller reads a page or sector of the free storage space, transmits a read result to an error correcting code engine, and determines the check result according to the number of error bit outputted from the error correcting code engine.

6. The data storage apparatus according to claim 1, wherein when programming the dummy data to the free storage space of the target block, the memory controller programs the dummy data to a part of the free storage space of the target block.

7. A method for preventing data error using a data storage apparatus, wherein the data storage apparatus comprises a memory and a memory controller, and the method for preventing data error is performed by a memory controller and comprises:

recording a read count of a target block of the memory;

performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and

programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

8. The method for preventing data error according to claim 7, wherein the target block comprises a plurality of pages or a plurality of sectors, and the read count of the target block indicates the sum of the read count of respective page or sector of the target block.

9. The method for preventing data error according to claim 7, wherein when determining whether the read count of the target block meets the condition, the determination is based on whether the read count of the target block is over a threshold value.

10. The method for preventing data error according to claim 7, wherein when performing the error bit check, the memory controller reads a page or sector of the free storage space and further determines whether a read result comprises a non-default value.

11. The method for preventing data error according to claim 7, wherein when performing the error bit check, the memory controller reads a page or sector of the free storage space, transmits a read result to an error correcting code engine, and determines the check result according to the number of error bit outputted from the error correcting code engine.

12. The method for preventing data error according to claim 7, wherein when programming the dummy data to the free storage space of the target block, the memory controller programs the dummy data to a part of the free storage space of the target block.