PLASMA PROCESSING METHOD

• US 20190326103A1
• Filed: 04/22/2019
• Published: 10/24/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Igarashi, Dai, Omi, Muneyuki, Ibuka, Rei, Murakami, Takahiro
• Granted Patent: US 10,784,088 B2
• Time in Patent Office: Days
• CPC Class Codes: F25B 2339/02 Details of evaporators
• CPC Class Codes: F25B 2400/0403 for the condenser
• CPC Class Codes: F25B 2400/0411 for the expansion valve or capillary tube
• CPC Class Codes: F25B 2600/2501 Bypass valves
• CPC Class Codes: F25B 39/02 Evaporators
• CPC Class Codes: F25B 49/02 for compression type machines, plants or systems
• CPC Class Codes: H01J 2237/002 Cooling arrangements
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01J 37/32568 Relative arrangement or disposition of electrodes; moving means
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67109 mainly by convection

Abstract

A plasma processing method capable of reducing an amount of deposit adhering to an upper electrode or removing the deposit from the upper electrode is provided. In the plasma processing method, the upper electrode of a capacitively coupled plasma processing apparatus is cooled. A supporting table including a lower electrode is provided within a chamber of the plasma processing apparatus. The upper electrode is provided above the supporting table. During the cooling of the upper electrode, a film of a substrate is etched by plasma generated within the chamber. The substrate is placed on the supporting table during the etching of the film. A negative bias voltage is applied to the upper electrode while the etching is being performed.

Claims

1. A plasma processing method performed in a capacitively coupled plasma processing apparatus, the plasma processing method comprising:

cooling an upper electrode of the plasma processing apparatus in which a chamber incorporating therein a supporting table including a lower electrode is provided and the upper electrode is provided above the supporting table;

etching a film of a substrate placed on the supporting table by plasma generated within the chamber during the cooling of the upper electrode; and

generating a negative bias voltage in the upper electrode during the etching of the film.

2. The plasma processing method of claim 1,

wherein a path having an inlet and an outlet is formed within the upper electrode, and the upper electrode constitutes an evaporator,

a compressor, a condenser and an expansion valve are connected in sequence between the outlet and the inlet of the path, and

a coolant is supplied into the path via the compressor, the condenser and the expansion valve in the cooling of the upper electrode.

3. The plasma processing method of claim 1, further comprising:

measuring an electric current flowing in the upper electrode.

4. The plasma processing method of claim 1,

wherein the film contains silicon, and

the plasma is generated from a processing gas including carbon, hydrogen and fluorine in the etching of the film.

5. The plasma processing method of claim 4,

wherein the film is a multilayered film having multiple silicon oxide films and multiple silicon nitride films alternately stacked on top of each other.

6. The plasma processing method of claim 1,

wherein the upper electrode comprises a ceiling plate configured to form and confine a space within the chamber,

the ceiling plate is made of silicon, and

in the generating of the negative bias voltage, a negative DC voltage is applied to the upper electrode or a high frequency power is supplied to the upper electrode such that the negative bias voltage is generated in the upper electrode.

7. The plasma processing method of claim 1,

wherein the upper electrode comprises a ceiling plate configured to form and confine a space within the chamber,

the ceiling plate is made of silicon oxide, and

in the generating of the negative bias voltage, a high frequency power is supplied to the upper electrode such that the negative bias voltage is generated in the upper electrode.