Structure and Method for Embedded Gettering in a Silicon On Insulator Wafer

• US 20190326128A1
• Filed: 04/20/2018
• Published: 10/24/2019
• Est. Priority Date: 04/20/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Pu-Fang, Lin, Shi-Chieh, Lu, Victor Y., Tu, Yeur-Luen
• Granted Patent: US 11,211,259 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/3226 of silicon on insulator
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Claims

1. A method of manufacturing a silicon-on-insulator (SOI) substrate, the method comprising:

forming an epitaxial layer over a first substrate;

depositing a gettering layer over the epitaxial layer;

bonding a second substrate to the gettering layer, wherein the second substrate comprises an insulating layer, and the insulating layer adjoins the gettering layer after bonding the second substrate; and

removing the first substrate.

2. The method of claim 1, further comprising oxidizing the second substrate to form the insulating layer prior to the bonding the second substrate to the gettering layer, wherein after the bonding the second substrate to the gettering layer, the insulating layer is interposed between an unoxidized portion of the second substrate and the gettering layer.

3. The method of claim 1, further comprising oxidizing the gettering layer prior to the bonding the second substrate.

4. The method of claim 1, wherein the bonding the second substrate comprises an annealing process performed at a temperature of between about 300°

C. and about 400°

C.

5. The method of claim 1, further comprising, prior to the forming the epitaxial layer, depositing a stop film over the first substrate.

6. The method of claim 5, wherein the stop film is interposed between and adjoins the first substrate and the epitaxial layer.

7. The method of claim 5, wherein the removing the first substrate comprises removing the stop film, and exposing the epitaxial layer.

8. A method of manufacturing a silicon-on-insulator (SOI) substrate, the method comprising:

depositing an etch stop layer over a dummy wafer;

growing an epitaxial silicon layer over the etch stop layer;

forming a gettering layer over the epitaxial silicon layer;

bonding an oxide layer of a main wafer to an oxidized portion of the gettering layer;

after bonding the oxide layer of the main wafer, removing the dummy wafer; and

after removing the dummy wafer, removing the etch stop layer.

9. The method of claim 8, wherein:

depositing the etch stop layer comprises depositing silicon germanium; and

forming the gettering layer comprises forming one of polysilicon, silicon nitride, silicon oxynitride, or silicon germanium.

10. The method of claim 8, further comprising thermally oxidizing the gettering layer prior to the bonding the oxide layer of the main wafer.

11. The method of claim 8, further comprising thermally oxidizing the main wafer to form the oxide layer prior to the bonding the oxide layer of the main wafer.

12. The method of claim 8, wherein the bonding the oxide layer of the main wafer comprises annealing at a temperature of between about 300°

C. and about 400°

C. for a duration of time between about 1 hour and about 3 hours.

13. The method of claim 8, wherein removing the dummy wafer comprises at least one of a grinding process or a planarizing process.

14. The method of claim 8, wherein removing the etch stop layer comprises a wet etch process.

15. A semiconductor device comprising:

a silicon substrate;

a buried oxide layer;

a gettering layer adjoining the buried oxide layer; and

an epitaxial silicon layer adjoining the gettering layer, wherein the gettering layer is interposed between the buried oxide layer and the epitaxial silicon layer.

16. The semiconductor device of claim 15, wherein the gettering layer comprises a first material and the buried oxide layer comprises an oxide of the first material.

17. The semiconductor device of claim 15, wherein the gettering layer comprises polysilicon.

18. The semiconductor device of claim 15, wherein the gettering layer comprises a nitride material.

19. The semiconductor device of claim 15, wherein the gettering layer comprises silicon oxynitride.

20. The semiconductor device of claim 15, wherein the gettering layer comprises silicon germanium.