THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20190326166A1
• Filed: 07/02/2019
• Published: 10/24/2019
• Est. Priority Date: 07/07/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Phil Ouk, AHN, Jaeyoung, LEE, Sangsoo
• Granted Patent: US 10,727,115 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.

Claims

1. A three dimensional (3D) semiconductor memory device comprising:

a substrate including a cell array region and a connection region;

a stack structure comprising a plurality of electrodes and a plurality of insulating layers vertically and alternately stacked on the substrate, the stack structure having a first staircase structure formed along a first direction on the connection region and a second staircase structure formed along a second direction crossing the first direction on the connection region, and

an etch stop layer covering the first and second staircase structures of the stack structure, the etch stop layer comprising an amorphous boron layer;

wherein the first staircase structure comprises a plurality of first stairs, each of the first stairs comprising adjacent two of the electrodes, and

wherein the second staircase structure comprises a plurality of second stairs, each of the second stairs comprising one of the electrodes,

wherein the first and second directions are parallel to a top surface of the substrate.

2. The semiconductor device of claim 1, wherein the etch stop layer has a substantially uniform thickness on sidewalls of the first stairs and the second stairs.

3. The semiconductor device of claim 1, further comprising:

a plurality of contact plugs respectively connected to the electrodes of the electrode structure,

wherein the plurality of contact plugs penetrate the etch stop layer on the connection region.

4. The semiconductor device of claim 3, wherein the plurality of contact plugs are arranged along the first and second directions.

5. The semiconductor device of claim 1, further comprising:

a first contact plug connected to a lowermost one of the electrodes; and

a second contact plug connected to an uppermost one of the electrodes,

wherein each of the first and second contact plugs includes an extended portion extending in a third direction perpendicular to the top surface of the substrate and a contacted portion protruding horizontally from the extended portion and disposed in the etch stop layer.

6. The semiconductor device of claim 1, further comprising:

a first contact plug connected to a lowermost one of the electrodes; and

a second contact plug connected to an uppermost one of the electrodes,

wherein a bottom surface of the first contact plug is located at a first distance from a top surface of the lowermost one of the electrodes, and

a bottom surface of the second contact plug is located at a second distance from a top surface of the uppermost one of the electrodes, the first distance being different from the second distance.

7. The semiconductor device of claim 6, wherein top surfaces of the first and second contact plugs are located at substantially the same level from the top surface of the substrate.

8. The semiconductor device of claim 1, further comprising:

a horizontal dielectric layer covering both a top surface and a bottom surface of the electrodes,

wherein the horizontal dielectric layer includes a material different from a material of the etch stop layer, and

wherein a portion of the horizontal dielectric layer contacts the etch stop layer.

9. The semiconductor device of claim 8, wherein the etch stop layer is thicker than the horizontal dielectric layer.

10. The semiconductor device of claim 1, wherein the amorphous boron layer contains about 90 to 100 atomic percent of boron.

11. A three dimensional (3D) semiconductor memory device comprising:

a substrate including a cell array region and a connection region adjacent to the cell array region in a first direction;

a stack structure comprising a plurality of electrodes and a plurality of insulating layers vertically and alternately stacked on the substrate, the stack structure having a staircase structure formed along the first direction on the connection region, the staircase structure comprising a plurality of first stairs, each of the first stairs comprising adjacent two of the electrodes; and

an etch stop layer covering sidewalls of the plurality of first stairs, etch stop layer comprising an amorphous boron layer.

12. The semiconductor device of claim 11, wherein sidewalls of the adjacent two of the electrodes are vertically aligned with each other.

13. The semiconductor device of claim 11, wherein the etch stop layer conformally covers the plurality of first stairs.

14. The semiconductor device of claim 11, further comprising:

a first contact plug connected to a lowermost one of the electrodes; and

a second contact plug connected to an uppermost one of the electrodes,

wherein each of the first and second contact plugs includes an extended portion extending in a second direction perpendicular to the top surface of the substrate and a contacted portion protruding horizontally from the extended portion and disposed in the etch stop layer.

15. The semiconductor device of claim 14, wherein the extended portion of the first contact plug has a first width and the extended portion of the second contact plug has a second width, the second width being different from the first width.

16. The semiconductor device of claim 11, further comprising:

a first contact plug connected to a lowermost one of the electrodes; and

a second contact plug connected to an uppermost one of the electrodes,

wherein the first contact plug has a first sidewall facing the etch stop layer and the second contact plug has a second sidewall facing the etch stop layer, and

wherein the first sidewall has at least one of a substantially vertical shape or a rounded shape and the second sidewall has an inclined shape.

17. The semiconductor device of claim 11, further comprising:

a first contact plug connected to a lowermost one of the electrodes; and

a second contact plug connected to an uppermost one of the electrodes,

wherein a bottom surface of the first contact plug is located at a first distance from a top surface of the lowermost one of the electrodes, and

a bottom surface of the second contact plug is located at a second distance from a top surface of the uppermost one of the electrodes, the first distance being different from the second distance.

18. The semiconductor device of claim 11, wherein the amorphous boron layer contains about 90 to 100 atomic percent of boron.

19. The semiconductor device of claim 11, further comprising:

a vertical structure on the cell array region and penetrating the stack structure; and

a horizontal dielectric layer disposed between the vertical structure and the electrodes and covering both a top surface and a bottom surface of each of the electrodes,

wherein a portion of the horizontal dielectric layer on the connection region is between the etch stop layer and top surfaces of the electrodes.

20. The semiconductor device of claim 19, wherein the horizontal dielectric layer includes a material different from a material of the etch stop layer.