FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME

• US 20190326176A1
• Filed: 07/01/2019
• Published: 10/24/2019
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: JANGJIAN, Shiu-Ko, YU, Ren-Hau, JENG, Chi-Cherng
• Granted Patent: US 10,832,959 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a first pair of gate spacers;

forming a high-k dielectric layer in an opening defined between a first gate spacer of the first pair of gate spacers and a second gate spacer of the first pair of gate spacers;

forming a plurality of metal layers over the high-k dielectric layer; and

forming a metal filler over the plurality of metal layers using a fluorine-based precursor, wherein fluorine from the fluorine-based precursor diffuses into at least one metal layer of the plurality of metal layers.

2. The method of claim 1, wherein the fluorine-based precursor comprises tungsten hexafluoride.

3. The method of claim 1, wherein forming the plurality of metal layers over the high-k dielectric layer comprises:

forming a first metal layer of the plurality of metal layers over the high-k dielectric layer, wherein;

the first metal layer comprises Al, and

a concentration of Al atoms in a first edge region of the first metal layer is different than a concentration of Al atoms in a middle region of the first metal layer.

4. The method of claim 3, wherein the first edge region is between the middle region and the first gate space.

5. The method of claim 3, wherein the middle region is between the first edge region and the first gate spacer.

6. The method of claim 3, wherein:

the concentration of Al atoms in the first edge region is greater than the concentration of Al atoms in the middle region,

a concentration of Al atoms in a second edge region of the first metal layer is greater than the concentration of Al atoms in the middle region, and

the middle region is between the first edge region and the second edge region.

7. The method of claim 1, wherein:

the high-k dielectric layer and the plurality of metal layers define a stacked structure, and

after the fluorine-based precursor diffuses into the at least one metal layer of the plurality of metal layers, a side wall of the stacked structure contains a first fluorine concentration and a bottom of the stacked structure contains a second fluorine concentration different than the first fluorine concentration.

8. The method of claim 7, wherein the first fluorine concentration is greater than the second fluorine concentration.

9. The method of claim 7, wherein the first fluorine concentration is substantially from 5 at % to 20 at % and the second fluorine concentration is substantially from 1 at % to 15 at %.

10. The method of claim 1, wherein:

forming the plurality of metal layers comprises forming the plurality of metal layers to overlie the first gate spacer,

forming the metal filler comprises forming the metal filler to overlie the first gate spacer, and

the method comprises performing a planarization process to expose the first gate spacer after forming the metal filler.

11. The method of claim 1, comprising:

forming a second pair of gate spacers;

forming a dielectric layer between the first pair of gate spacers and the second pair of gate spacers; and

performing a planarization process to remove a first portion of the dielectric layer, wherein a top surface a second portion of the dielectric layer remaining between the first pair of gate spacers and the second pair of gate spacers after the planarization process is concave.

12. A method for forming a semiconductor device, the method comprising:

forming a first pair of gate spacers;

forming a plurality of metal layers in an opening defined between a first gate spacer of the first pair of gate spacers and a second gate spacer of the first pair of gate spacers, wherein the plurality of metal layers define a stacked structure; and

forming a metal filler over the stacked structure using a fluorine-based precursor, wherein;

the stacked structure has a first fluorine concentration prior to forming the metal filler,

the stacked structure has a second fluorine concentration after forming the metal filler, and

the second fluorine concentration is greater than the first fluorine concentration.

13. The method of claim 12, wherein:

after forming the metal filler, a concentration of fluorine present in a side wall of the stacked structure is different than a concentration of fluorine present in a bottom of the stacked structure.

14. The method of claim 13, wherein the concentration of fluorine present in the side wall is substantially from 5 at % to 20 at % and the concentration of fluorine present in the bottom is substantially from 1 at % to 15 at %.

15. The method of claim 13, wherein the concentration of fluorine present in the side wall is greater than the concentration of fluorine present in the bottom.

16. The method of claim 12, wherein forming the plurality of metal layers comprises:

forming a first metal layer of the plurality of metal layers in the opening, wherein;

the first metal layer comprises Al, and

a concentration of Al atoms in a first edge region of the first metal layer is different than a concentration of Al atoms in a middle region of the first metal layer.

17. The method of claim 16, wherein:

the concentration of Al atoms in the first edge region is greater than the concentration of Al atoms in the middle region,

a concentration of Al atoms in a second edge region of the first metal layer is greater than the concentration of Al atoms in the middle region, and

the middle region is between the first edge region and the second edge region.

18. A method for forming a semiconductor device, the method comprising:

forming a first pair of gate spacers;

forming a high-k dielectric layer in an opening defined between a first gate spacer of the first pair of gate spacers and a second gate spacer of the first pair of gate spacers;

forming a plurality of metal layers over the high-k dielectric layer; and

diffusing fluorine into at least one metal layer of the plurality of metal layers.

19. The method of claim 18, wherein:

the high-k dielectric layer and the plurality of metal layers define a stacked structure, and

after diffusing the fluorine into the at least one metal layer of the plurality of metal layers, a side wall of the stacked structure contains a first fluorine concentration and a bottom of the stacked structure contains a second fluorine concentration different than the first fluorine concentration.

20. The method of claim 19, wherein the first fluorine concentration is substantially from 5 at % to 20 at % and the second fluorine concentration is substantially from 1 at % to 15 at %.