INTEGRATING A PLANAR FIELD EFFECT TRANSISTOR (FET) WITH A VERTICAL FET
First Claim
1. A semiconductor structure comprising:
- a vertical field-effect transistor (FET), wherein the vertical FET comprises a first semiconductor and a vertical gate perpendicular to and extending across the first semiconductor; and
a planar FET integrated with the vertical FET, wherein the planar FET comprises a second semiconductor and a planar gate perpendicular to and extending across the second semiconductor;
wherein a top of the vertical gate and a top of the planar gate are co-planar; and
wherein the semiconductor structure is optimized for both input/output (I/O) devices and memory and logic devices.
1 Assignment
0 Petitions
Accused Products
Abstract
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
-
Citations
6 Claims
-
1. A semiconductor structure comprising:
-
a vertical field-effect transistor (FET), wherein the vertical FET comprises a first semiconductor and a vertical gate perpendicular to and extending across the first semiconductor; and a planar FET integrated with the vertical FET, wherein the planar FET comprises a second semiconductor and a planar gate perpendicular to and extending across the second semiconductor; wherein a top of the vertical gate and a top of the planar gate are co-planar; and wherein the semiconductor structure is optimized for both input/output (I/O) devices and memory and logic devices. - View Dependent Claims (2, 3, 4, 5, 6)
-
Specification