SEMICONDUCTOR DEVICES

• US 20190326182A1
• Filed: 07/03/2019
• Published: 10/24/2019
• Est. Priority Date: 05/22/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: ZHOU, Fei
• Granted Patent: US 11,646,236 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor structure is provided. The semiconductor structure includes a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region. A first work function layer is formed on the base substrate in the second region. A second work function layer is formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

Claims

1. A semiconductor device, comprising:

a base substrate including a first device region, a second device region, and a transition region separating the first region from the second region;

a first work function layer formed on the base substrate in the second region; and

a second work function layer formed on the base substrate in the first region and the transition region, and on the first work function layer in the second region.

2. The semiconductor device according to claim 1, further including:

a high-k dielectric layer formed in the first region between the base substrate and the second work function layer and in the second region between the base substrate and the first work function layer, without being on the transition region.

3. The semiconductor device according to claim 1, wherein:

a width of the transition region is in a range of approximately 36 nm to 86 nm.

4. The semiconductor device according to claim 1, wherein:

a plurality of first devices are formed in the first region; and

a plurality of second devices are formed in the second region.

5. The semiconductor device according to claim 4, wherein:

a type of the plurality of first devices formed in the first region is different from a type of the plurality of second devices formed in the second region.

6. The semiconductor device according to claim 5, wherein:

the plurality of first devices are N-type metal-oxide-semiconductor (NMOS) devices; and

the plurality of second devices are P-type metal-oxide-semiconductor (PMOS) devices.

7. The semiconductor device according to claim 6, wherein:

the first work function layer is made of at least one of TiN, TaN, and TiSiN.

8. The semiconductor device according to claim 1 wherein:

a thickness of the first work function layer is in a range of approximately 25 Å and

50 Å

.

9. The semiconductor device according to claim 6, wherein:

the second work function layer is made of at least one of TiAl, Al, TiC, and TiCAl.

10. The semiconductor device according to claim 1 wherein:

a thickness of the second work function layer is in a range of approximately 30 Å and

60 Å

.

11. The semiconductor device according to claim 1, wherein:

the base substrate includes a substrate and a plurality of discrete fin structures formed on the substrate.